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JPH0243748A Expired / Lapsed JP ⏱️ 0.0 years remaining

Packaging of integrated circuit chip

Assignee: Ricoh Co Ltd
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Filing: 1988-08-04
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Granted: —
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Expires: 2008-08-04
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Abstract

Abstract PURPOSE:To package an IC chip provided with pads, the pitch being smaller than in a conventional design, onto a substrate using the flip chip bonding method without inducing bonding defects by a method wherein a low-melting solder bump is formed on a large pad and a high-melting solder bump is formed on a small pad prior to packaging, both on the IC chip. CONSTITUTION:Prior to packaging an IC chip 9 onto a substrate 17 using the flip chip bonding method, a large pad 10 and a small pad 11 are provided on the IC chip 9, a low-melting solder bump 14 is formed on the large pad 10, and a high-melting solder bump 15 is formed on the small pad 11. For example, the IC chip 9 is mounted on the substrate 17, the entirety is placed in a solder reflow oven and then heated to the melting point of the low-melting solder bump 14, whereby the large pad 10 of the IC chip 9 is bonded to a large pad 18 on the substrate 17. The temperature in the oven is elevated next to the melting point of the high-melting solder bump 15, whereby the small pad 11 of the IC chip 9 is bonded to a small pad 19 on the substrate 17.

Inventors

  • 👤 Shunpei Tamaoki
  • 👤 俊平 玉置

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 20:28
CPC Classifications
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