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JPH0216752A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1988-07-05
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Granted: —
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Expires: 2008-07-05
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Abstract

Abstract PURPOSE:To realize even the flatness of isolation regions by causing the size within a prescribed range to be applicable to widths of the isolation regions in a semiconductor having insulator embedded type element isolation regions. CONSTITUTION:An SiO2 film 4, an poly-Si film 3, and then, an SiO2 film 2 and a resist film 6 which are not exhibited in drawing are formed on an Si substrate 5. Films 2, 3 and 4 are etched by using the resist film 6 as a mask and the substrate 5 is etched by using the film 2 as the mask to form element isolation regions 7. An SiO2 film 8 is formed with a CVD process and, after an embedded resist 9 is formed on the isolation regions having wide widths, a leveled resist 10 makes the whole surface flat. When W represents each width of the isolation regions 7, (t) is the thickness of each side wall part of the film 8, H is mask alignment accuracy, (m) is a minimum pattern size, the following relationship applies: W>=2t+2E+(m) or W<=2(t)+E. Moreover, this semiconductor is free from isolation regions having incomplete widths and, if the groove in the film 8 is deep, the embedded resist 9 is formed without fail. After forming the resist 10, isolation and element parts are formed by the technique of a known method.

Inventors

  • 👤 Ichiro Nakao
  • 👤 中尾 一郎
  • 👤 Mikio Nishio
  • 👤 西尾 幹夫

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 05:41
CPC Classifications
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