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JPH02126684A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Toshiba Corp
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Filing: 1988-11-07
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Granted: —
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Expires: 2008-11-07
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Abstract

Abstract PURPOSE:To prevent a pattern of a high-melting-point metal material from being cut by a method wherein a first gate electrode, a second gate insulating film and one part of a second gate electrode inside an identical cell are formed in a self- alignment manner, second gate electrodes in other cells after that are connected by the use of a third electrode layer on a third insulating film which has been left. CONSTITUTION:A polysilicon layer 104' to be used as a first gate electrode is formed in self-alignment with a polysilicon layer 106' which is formed directly on it; it is separated far away by an insulating layer 111; since the polysilicon layer 104' is not constituted so as to be surrounded by the polysilicon layer 106', an angle part and a protruding part are not formed; accordingly, a breakdown strength characteristic and a memory retention characteristic are enhanced. As long as a third wiring electrode layer 112 is connected to the polycrystalline silicon layer 106', it can run at an arbitrary width and in an arbitrary position; a degree of freedom for a designing operation is increased. In addition, since this assembly is flattened by the insulating layer 111, a difference in level between a cell part and a part between cells is reduced; when the third wiring layer 112 is constituted of a silicide or a polycide, it is possible to completely prevent a disconnection by the difference in level.

Inventors

  • 👤 Kuniyoshi Yoshikawa
  • 👤 吉川 邦良

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 17:37
CPC Classifications
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