vertical field effect transistor

Abstract

Abstract PURPOSE:To remove the edge of a gate electrode apt to cause electric field concentration so as to enable high withstand voltage by equipping a polysilicon gate electrode having low resistivity on a channel part and providing polysilicon having high resistivity continuously and evenly with the polysilicon gate electrode above between base areas. CONSTITUTION:As an element forming substrate, a low concentration N<->-type drain area 2 formed on a high concentration substrate 1 to become a drain by epitaxial growth is used. A P type base 3 and an N<+> type source 4 are made in self-alignment with polysilicon gate electrodes 5 and 5' as a mask, and as for the polysilicon gate electrodes 5 and 5', they are made into a gate electrode 5' having high resistivity above between the P bases 3 and a gate electrode 5 having low resistivity above other parts. In this case, the polysilicon gate electrode 5 having low resistivity may be formed before or after the P type base 3 and the N<+> type source 4. Thereafter, an insulation film 6, a source electrode 7 and a drain electrode 8 are formed. Hereby, high withstand voltage becomes possible.

Inventors

• 👤 Yoshitomo Takahashi
• 👤 美朝 高橋

Bibliographic Details