memory circuit

Abstract

Abstract PURPOSE:To detect the partial disconnection of a bit line by connecting between neighboring bit lines by a MOS transistor in a memory array including a memory cell. CONSTITUTION:In case of evaluating the bit lines the inverse of BL1 and BL2, information is inputted setting BL0, the inverse of BL1, the inverse of BL2, BL3, and the inverse of BLN at VCC and the inverse of BL0, BL1, BL2, the inverse of BL3, and BLN at VSS. A test signal TBL is inputted as the VCC. When the partial disconnection is generated in the center of the inverse of the bit line BL1, a sense amplifier SA near to the center of the inverse of BL1 is set at VCC, however, a right part of the center is set at the VSS by a FETM2 and a sense amplifier SA2. It is possible to decide a defect by operating a word line WL at the part since the defect is generated at the part. Since the continuity resistance of the FETM2 is set sufficiently larger than the operating resistance of the sense amplifier and the resistance of the bit line, a sample in which no partial disconnection is generated is operated normally, and the defect is generated when the incidental resistance of the part where the partial disconnection is generated becomes larger than the operating resistance of the FET, thereby, the partial disconnection can be decided.

Inventors

• 👤 Kazumasa Yanagisawa
• 👤 一正 柳沢

Bibliographic Details