Manufacture of semiconductor device

Abstract

Abstract PURPOSE:To prevent the yield of a large step with a sacrifical interlayer film and to make it possible to flatten a multilayer interconnection structure, by using etchant whose etching rate for a dummy film is slower than for an interlayer insulating film, and etching the interlayer insulating film together with the dummy film. CONSTITUTION:A first metal wiring 14 is patterned. Then, phosphorus mixed silicon glass(PSG) is deposited, and a sacrifical interlayer insulating film 15 having large surface step parts is obtained. Resist incorporating a carbon based organic material is applied on the irregular insulating film. Baking is performed at 160 deg.C for 30 minutes, and flow treatment is performed. Thus a dummy film 16 is provided. The mixing ratio of CHF3 gas for the PSG and O2 gas for the resist is set so that the ratio between the etching rate of the PSG and the etching rate of the resist becomes 1.5 in etchant gas. The dummy film 16 and the sacrifical interlayer insulating film 15 are flatly etched away with said etchant gas down to the upper surface of the upper first metal wiring layer 14. Finally, all the remaining dummy film 16 is released and removed, and a new interlayer film 17 is deposited.

Inventors

• 👤 Akinobu Nakahiro
• 👤 中廣　顕伸

Bibliographic Details