Patent JP2003174141A successfully refreshed from Google Patents.
← Back to Patent Explorer
JP2003174141A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device and manufacturing method thereof

Assignee: DT Circuit Technology Co Ltd
•
Filing: 2002-08-15
•
Granted: —
•
Expires: 2022-08-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Translated from Japanese (57)【要約】 【課題】 機械的強度や耐湿性といった半導体装置とし ての信頼性が高く、しかも多層板表面全体に配線パター ンを形成して集積度を向上させることのできる半導体装 置及びその製造方法を提供する。 【解決手段】 2層板52の配線パッド41b,41b 上に導体バンプ60,60,…を形成し、バリアメタル 層61とAu層62を形成し、その上に半導体素子70 を実装する。更にその上に開口部31aを設けたプリプ レグ31と、もう一つの2層板54を位置合わせし、ヒ ートプレスする。得られた半導体装置1の表面には半導 体素子70の周囲に充填した絶縁性樹脂と2層板54と の境界面は現れない。 PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability as a semiconductor device, such as mechanical strength and moisture resistance, capable of improving a degree of integration by forming a wiring pattern on the entire surface of a multilayer board, and manufacturing thereof. Provide a method. SOLUTION: Wiring pads 41b of a two-layer board 52 Are formed thereon, a barrier metal layer 61 and an Au layer 62 are formed, and a semiconductor element 70 is formed thereon. Implement Further, the prepreg 31 having the opening 31a provided thereon and another two-layer plate 54 are aligned and heat-pressed. No boundary surface between the insulating resin filled around the semiconductor element 70 and the two-layer plate 54 appears on the surface of the obtained semiconductor device 1.

Inventors

  • 👤 Hiroyuki Hirai
  • 👤 浩之 平井
  • 👤 Yoshitaka Fukuoka
  • 👤 義孝 福岡

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 11:57
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/073; H10W74/00; H10W74/10; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag