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Method for manufacturing semiconductor device

Assignee: Seiko Epson Corp
•
Filing: 1999-03-05
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Granted: —
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Expires: 2019-03-05
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Abstract

Abstract Translated from Japanese (57)【要約】 【課題】複数の半導体チップの機能を有し小型で実装面 積が小さく複合的で多機能な半導体装置を製造する方法 を提供する。 【解決手段】異なる機能を持つ半導体チップ1−1,1 −2,1−3を積層し、3次元的に電気的接続を行う。 電極パッド部3−1に開けたスルーホールに、半田めっ きを施した金属細線ワイヤー4−1を挿入し、そのの ち、リフロー炉で半田を溶融させて接合する。 (57) Abstract: Provided is a method for manufacturing a composite multifunctional semiconductor device having a small size, a small mounting area, and a function of a plurality of semiconductor chips. Semiconductor chips having different functions -2 and 1-3 are stacked and three-dimensionally electrically connected. The thin metal wire 4-1 plated with solder is inserted into the through hole opened in the electrode pad portion 3-1, and then the solder is melted and joined in a reflow furnace.

Inventors

  • 👤 Kuniyasu Matsui
  • 👤 邦容 松井
  • 👤 Shuji Koeda
  • 👤 周史 小枝

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 18:29
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/722

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