Method and apparatus for frequency multiplying an electrical signal

Claim 4

A multiplier circuitry for multiplying an input electrical signal by a multi-level multiplier, comprising: (a) an oscillator for producing an oscillation signal the frequency of which is a multiple of the 15 fundamental frequency of said multi-ievel multiplier, said oscillation frequency having a predetermined phase; (b) a first signal generator responsive to said oscillation signal for producing an asymmetrical square wave signal having a frequency which equals twice the fundamental frequency of said multi- level multiplier, a predetermined duty cycle and a predetermined phase; (c) a frequency divider responsive to said asymmetrical square wave signal from said first signal generator for dividing the frequency of said asymmetrical square wave signal by two, said frequency divider producing at least one output signal; (d) a second signal generator responsive to said input electrical signal, to said asymmetrical square wave signal from said first signal generator and to said output signal of said frequency divider, 25 for multiplying said input electrical signal by said asymmetrical square wave signal and substantially by a symmetrical square wave signal, which is obtained from said output signal of said frequency divider, or vice versa to produce an output product signal.

Claim 5

A multiplier circuitry as claimed in Claim 4, wherein said oscillator comprises a voltage controlled oscillator responsive to the voltage of said input electrical signal.

Claim 6

A multiplier circuitry as claimed in Claim 4, wherein said oscillator comprises a current controlled oscillator responsive to the current of said input electrical signal.

Claim 7

A multiplier circuitry as claimed in Claim 4, wherein said oscillator comprises a saw tooth wave signal generator responsive to said input electrical signal.

Claim 8

A multiplier circuitry as claimed in Claim 4, wherein said first signal generator comprises a 35 divide-by-three frequency divider.

Claim 9

A multiplier circuitr as claimed in Claim 4, wherein said first signal generator comprises a monostable multivibrator.

Claim 10

A multiplier circuitry as claimed in Claim 4, wherein said first signal generator comprises a threshold circuit responsive to the output signal of said oscillator and to a reference signal.

Claim 11

A multiplier circuitry as claimed in Claim 4, wherein said frequency divider comprises a flip- flop.

Claim 12

A multiplier circuitry as claimed in Claim 4, wherein said second signal generator comprises: (a) an unbalanced multiplier for multiplying said input electrical signal by said asymmetrical square wave signal from said first signal generator to produce a primary product signal; and (b) a balanced multiplier for multiplying said primary product signal by said symmetrical square wave signal.

Claim 13

A multiplier circuitry as claimed in Claim 12, wherein said unbalanced multiplier comprises a switching circuit controlled by said asymmetrical square wave signal.

Claim 14

A multiplier circuitry as claimed in Claim 12, wherein said balanced multiplier comprises a 50 phase splitter responsive to said primary product signal for producing two output signals having opposite phase with each other, and a gang switching circuit of double- pole clouble-throw type for switching over said two output signals in accordance with said output signal of said frequency divider, or its inverted signal.

Claim 15

A multiplier circuitry as claimed in Claim 12, wherein said balanced multiplier comprises a 55 phase splitter responsive to said primary product signal for producing two output signals having opposite phase with each other, and a pair of switching circultsfor respectively switching over said two output signals in accordance with said output signal of said frequency divider and its inverted signal.

Claim 16

A multiplier circuitry as claimed in Claim 4, wherein said second signal generator comprises: (a) a first unbalanced multiplier for multiplying said input electrical signal by said asymmetrical 60 square wave signal from said first signal generator to produce a primary product signal; (b) a second unbalanced multiplier for multiplying said primary product signal by said output signal of said frequency divider to produce an output signal; (c) a third unbalanced multiplier for multiplying said primary product signal by an inverted signal of said output signal of said frequency divider to produce an output signal; and 18 GB 2 052 218 A 18 (d) a subtracter responsive to the output signals of said second and third unbalanced multipliers for producing at least one output signal indicative of the difference between the output signals of said second and third unbalanced multipliers.

Claim 17

A multiplier circuitry as claimed in Claim 4, wherein said second signal generator comprises: (a) a first unbalanced multiplier for multiplying said input electrical signal by said output signal of 5 said frequency divider to produce an output signal; (b) a second unbalanced multiplier for multiplying input electrical signal by an inverted signal of said output signal of said frequency divider to produce an output signal; (c) a third unbalanced multiplier for multiplying said output signal of said first unbalanced multiplier by said asymmetrical square wave signal from said first signal generator to produce an 1 P output signal; (d) a fourth unbalanced multiplier for multiplying said output signal of said second unbalanced multiplier by said asymmetrical square wave signal from said first signal generator to produce an output signal; and (e) a subtracter responsive to the output signals of s3id third and fourth unbalanced multipliers for 15 producing at least one output signal indicative of the difference between the output signals of said third and fourth unbalanced multipliers.

Claim 18

A multiplier circuitry as claimed in Claim 4, wherein said second signal generator comprises: (a) a balanced multiplier for multiplying said input electrical signal by said symmetrical square wave signal obtained from said output signal of said frequency divider and/or its inverted signal, said 20 balanced multiplier producing first and second balanced output signals at its two output terminals; and (b) a switching circuit interposed between said two output terminals of said balanced multiplier for making a short circuit in accordance with said asymmetrical square wave signal from said first signal generator.

Claim 19

A multiplier circuitry as claimed in Claim 18, wherein said balanced multiplier comprises a 25 phase splitter responsive to said input electrical signal for producing two output signals having opposite phase with each other, and a gang switching circuit of double- pole double-throw type for switching over said two output signals in accordance with said output signal of said frequency divider or its inverted signal.

Claim 20

A multiplier circuitry as claimed in Claim 18, wherein said balanced multiplier comprises a 30 phase splitter responsive to said input electrical signal for producing two output signals having opposite phase with each other, and a pair of switching circuits for respectively switching over said two output signals in accordance with said output signal of said frequency divider and its inverted signal.

Claim 21

A multiplier circuitry as claimed in Claim 4, wherein said second signal generator comprises: (a) a phase splitter responsive to said input electrical signal for producing first and second output signals having opposite phase with each other; (b) a gang switching circuit of triple-pole double-throw type for switching over said first and second output signals from said first signal generator, said output signal of said frequency divider and the inverted signal of said output signal of said frequency divider being fed to said gang switching circuit as switching control signals, these three switching control signals respectively assuming high 40 and low levels, the high level voltage of said asymmetrical square wave signal from said first signal generator being higher than the high level voltage of the remaining switching control signals; and (c) an adder-distributor having first and second input terminals and first and second output terminals, said first and second output terminals being respectively connected to first and second output terminals of said second signal generator, said first and second output signals of said phase 45 splitter being respectively fed to said first and second output terminals of said second signal generator when the voltage of said output signal of said frequency divider is the highest among said three switching control signals, said first and second output signals of said phase splitter being respectively fed to said first and second input terminals of said adder-distributor when the voltage of said asymmetrical square wave signal is the highest among said three switching control signals, and said 50 first and second output signals of said phase splitter being respectively fed to said second and first output terminals of said second signal generator when the voltage of said inverted signal is the highest among said three switching control signals.

Claim 22

A multiplier circuitry as claimed in Claim 14, 15, 19, 20 or 2 1, wherein said phase splitter comprises: (a) a first transistor having a base electrode for receiving an input signal; (b) a second transistor having a base electrode connected via a bias source to ground; (c) a series circuit of two resistors, said series circuit being interposed between the base electrodes of said first and second transistors; and (d) a constant-current source connected between a junction connecting said two resistors, and 60 ground.

Claim 23

A multiplier circuitry as claimed in Claim 19, 20 or21, wherein said phase splitter comprises: (a) a first transistor having a base electrode for receiving an input signal; (b) a second transistor having a base electrode connected via a bias source to ground; i 19 GB 2 052 218 A 19 and (c) a first resistor connected between the emitter electrodes of said first and second transistors; (d) second and third resistors respectively interposed between the emitter electrodes of said first and second transistors, and ground.

Claim 25

An FM stereo multiplex decoding system for demodulating a composite stereo signal obtained by an FM detector, comprising: (a) an oscillator for producing a signal having a frequency which is a multiple of a suppressed sub 20 carrier wave of said composite stereo signal, and a predetermined phase; (b) a signal generator responsive to the output signal of said oscillator for producing an asymmetrical square wave signal having a frequency which equals twice the frequency of said suppressed sub carrier wave, a predetermined duty cycle and a predetermined phase; (c) a frequency divider for dividing the frequency of said asymmetrical square wave signal by two; 25 and (d) a stereo demodulator for multiplying said composite stereo signal by said asymmetrical square wave signal, and subsequently by the output signal of said frequency divider or vice versa for obtaining a difference component (L-R) and an inverted difference component (R-L) of the left and right channel signals (L) and (R), said stereo demodulator having a matrix means for matrixing said 30 composite stereo signal, said difference component (L-R) and said inverted difference component (R-L) to demodulate said left and right channel signals (L) and (R) respectively.

Claim 26

An FM stereo multiplex decoding system for demodulating a composite stereo signal obtained by an FM detector, comprising: (a) an oscillator the oscillation frequency of which is controllable; (b) a signal generator responsive to the output signal of said oscillator for producing an asymmetrical square wave signal having a predetermined duty cycle and a predetermined phase; (c) a first frequency for dividing the frequency of said asymmetrical square wave signal by two; (d) a second frequency divider for dividing the frequency of the output signal of said first frequency divider by two; (e) a gate circuit responsive to said asymmetrical square wave signal and to said output signal of said first frequency divider for producing a square wave signal having the same frequency as said output signal of said first frequency divider and a predetermined duty cycle; (f) a phase comparator responsive to said composite stereo signal having at least a pilot signal component, to the output signal of said second frequency divider and to the output signal of said gate 45 circuit for multiplying said composite stereo signal by said output signal of said gate circuit and subsequently by said output signal of said second frequency divider or vice versa to produce a product signal; (g) a low pass filter for passing a low frequency component of the output signal of said phase comparator; (h) a d.c. amplifier responsive to the output signal of said low pass filter to produce an output signal which is fed to an input terminal of said oscillator to control the oscillation frequency thereof, said oscillator, signal generator, first and second frequency dividers, gate circuit, phase comparator, low pass filter and d.c. amplifier constituting a phase locked loop so that the frequency of said asymmetrical square wave signal produced by said signal generator equals twice the frequency of a 55 suppressed sub carrier wave of said composite stereo signal, while the frequency of the output signal of said first frequency divider equals the frequency of said suppressed sub carrier signal; (i) a stereo demodulator for multiplying said composite stereo signal by said asymmetrical square wave signal from said signal generator, and subsequently by the output signal of said first frequency divider or vice versa for obtaining a difference component (L-R) and an inverted difference component 60 (R-Q of the left and right channel signals (L) and (R), said stereo demodulator having a matrix means for matrixing said composite stereo signal, said difference component (L-R) and said inverted difference component (R-L) to demodulate said left and right channel signals (L) and (R) respectively.

Claim 27

An FM stereo multiplex decoding system as claimed in Claim 26, wherein said phase comparator comprises: GB 2 052 218 A 20 (a) a first multiplier for multiplying said pilot signal component by said output signal of said gate circuit to produce a product signal; and (b) a second multiplier for multiplying said product signal from said first multiplier by said output signal of said second frequency divider.

Claim 28

An FM stereo multiplex decoding system as claimed in Claim 26, wherein said phase comparator comprises: (a) first and second gate circuits respectively responsive to the output signal of said gate circuit and to the output signal of said second frequency divider for producing respective output signals; (b) first and second multipliers for respectively multiplying said pilot signal component by said output signal of said first gate circuit and subsequently by said output signal of said second gate circuit 19 or vice versa; and (c) a subtracter responsive to the output signals of said first and second multipliers tor producing an output signal indicative of the difference between the output signals of said first and second multipliers.

Claim 29

An FM stereo multiplex decoding system as claimed in Claim 28, wherein said low pass filter comprises a capacitor connected between the output terminals of said first and second multipliers.

Claim 31

A multiplier circuitry for multiplying an input electrical signal by a multi-level multiplier substantially as hereinbefore described with reference to the accompanying drawings Figs. 1 to 11.

Claim 33

An FM stereo multiplex decoding system for demodulating a composite stereo signal obtained by an FM detector substantially as hereinbefore described with reference to the accompanying drawings Figs. 13 to 19. Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1981. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 'I AY, from which copies maybe obtained. 4 l'. 1