Digital synchronisation arrangements for time multiplex transmission receivers
Abstract
Abstract 1,069,650. Multiplex pulse signalling. TELEFUNKEN PATENTVERWERTUNGSG.m.b.H. Dec. 3, 1963 [Dec. 11, 1962], No. 47688/63. Heading H4L. In a synchronizing arrangement for a receiver in a time division multiplex pulse transmission system, the incoming pulses are supplied via a regenerator. RV to a shift register SR. The synchronizing signal consists of.alternate binary 1 and binary 0 in successive frames and during the synchronizing period the appropriate stage (K1) of the register is interrogated by means of a. pulse applied to line S to see if it contains the correct signal at the expected time. When a binary 1 is present at stage KI and coincides with a pulse on line S a bistable device KI is set via AND gate Ud1. during the next synchronizing period the signal at stage 1 should be binary 0 and if this is so an output from bi-stable circuit, KI is passed via the INHIBIT gate Jnh and AND gate Ud2 to set a bistable device KII. Thus a binary counter Z is switched via an AND gate UD3 to its first position and at the same time a signal on line RS resets the bi-stable circuits. Similarly, after each pair of frames the counter Z is stepped to its next position and at its final, i.e. eighth position, a signal is passed via AND gate UDZ to set the channel distributer into operation and it remains in operation as long as the synchronizing signals appear at the correct time and hold the counter Z in its final position. If the correct synchronizing signal does not appear at the expected time the counter Z is switched back one or more steps by the signal on line S. To ensure that only a repeated number of successive false synchronizing signals can cause switching back of the counter Z it may be in the form of a forwardsbackwards counter arranged to count one step forward for a correct signal and two steps backward for an incorrect signal, a new synchronizing sequence being initiated only if the zero position is reached.
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