← Back to Patent Explorer
FR2565031A1 Expired / Lapsed FR ⏱️ 0.0 years remaining

METHOD FOR PRODUCING A SHIELD BETWEEN TWO SUB-ASSEMBLIES OF A MICROCIRCUIT AND APPLICATION OF THIS METHOD TO THE PRODUCTION OF A MONOLITHIC INTEGRATED CIRCUIT COMPRISING TWO SUB-ASSEMBLIES THUS ISOLATED

Assignee: Laboratoires dElectronique Philips SAS
•
Filing: 1984-05-25
•
Granted: —
•
Expires: 2004-05-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Translated from French PROCEDE DE REALISATION D'UN BLINDAGE ENTRE DEUX SOUS-ENSEMBLES D'UN MICROCIRCUIT, CARACTERISE EN CE QU'IL COMPREND LES ETAPES DE : A.PREPARATION D'UN SUBSTRAT MONOCRISTALLIN SEMI-CONDUCTEUR, DESTINE A RECEVOIR UN CIRCUIT INTEGRE MONOLITHIQUE FORME DE PLUSIEURS SOUS-ENSEMBLES; B.DELIMITATION D'UNE ZONE DE MASSE EN SURFACE DU SUBSTRAT ENTRE LES SOUS-ENSEMBLES DEVANT ETRE ISOLES PAR BLINDAGE; C.REALISATION D'UNE GRAVURE SUR LA FACE ARRIERE DU SUBSTRAT DE MANIERE A DIMINUER L'EPAISSEUR DE CE DERNIER DANS UNE ZONE CORRESPONDANT SUR LA FACE ARRIERE AU MOINS A LA ZONE DE MASSE DEFINIE SUR LA FACE AVANT; D.REALISATION PAR GRAVURE DE LA FACE ARRIERE DE PASSAGES FAISANT COMMUNIQUER LA FACE ARRIERE ET LA FACE AVANT DU SUBSTRAT, DANS LA ZONE D'EPAISSEUR REDUITE; E.METALLISATION, PAR UN METAL CONVENANT A FORMER UN PLAN DE MASSE, DE LA ZONE DELIMITEE A CET EFFET SUR LA FACE AVANT, DE TOUT OU PARTIE DE LA FACE ARRIERE INCLUANT LA ZONE D'EPAISSEUR REDUITE, AINSI QUE DES PAROIS DES PASSAGES, DE MANIERE A OBTENIR LA LIAISON ELECTRIQUE ENTRE LE PLAN DE MASSE DE LA FACE AVANT ET LA METALLISATION ARRIERE; F.UTILISATION DE CE PLAN DE MASSE COMME MASSE DES SOUS-ENSEMBLES DU CIRCUIT INTEGRE. APPLICATION : REALISATION D'UNE TETE DE RECEPTION D'ANTENNE HYPERFREQUENCE MONOLITHIQUEMENT INTEGREE. PROCESS FOR REALIZING A SHIELD BETWEEN TWO SUB-ASSEMBLIES OF A MICROCIRCUIT, CHARACTERIZED IN THAT IT INCLUDES THE STEPS OF: A.PREPARATION OF A SEMICONDUCTOR MONOCRISTALLINE SUBSTRATE, INTENDED TO RECEIVE A MORE MONOLITHIC INTEGRATED CIRCUIT SUB-ASSEMBLIES; B. DELIMITATION OF A GROUND AREA ON THE SURFACE OF THE SUBSTRATE BETWEEN THE SUB-ASSEMBLIES TO BE INSULATED BY SHIELDING; C. MAKING AN ENGRAVING ON THE REAR SIDE OF THE SUBSTRATE SO AS TO REDUCE THE THICKNESS OF THE SUBSTRATE IN AN AREA CORRESPONDING ON THE REAR SIDE AT LEAST TO THE MASS ZONE DEFINED ON THE FRONT SIDE; D. REALIZATION BY ENGRAVING OF THE REAR SIDE OF PASSAGES MAKING THE REAR SIDE AND THE FRONT SIDE OF THE SUBSTRATE COMMUNICATE IN THE AREA OF REDUCED THICKNESS; E. METALIZATION, BY A METAL SUITABLE TO FORM A GROUND PLAN, OF THE ZONE DELIMITED FOR THIS EFFECT ON THE FRONT SIDE, OF ALL OR PART OF THE REAR SIDE INCLUDING THE ZONE OF REDUCED THICKNESS, AS WELL AS OF THE WALLS OF THE PASSAGES SO AS TO OBTAIN THE ELECTRICAL LINK BETWEEN THE EARTH PLAN OF THE FRONT PANEL AND THE REAR METALLIZATION; F. USE OF THIS GROUND PLAN AS GROUND OF THE SUB-ASSEMBLIES OF THE INTEGRATED CIRCUIT. APPLICATION: REALIZATION OF A MONOLITHICALLY INTEGRATED HYPERFREQUENCY ANTENNA RECEPTION HEAD.

Inventors

  • 👤 Christian Gilbert Je Kermarrec
  • 👤 Pierre Jean-Marie Kaikati

Bibliographic Details

Application Number —
Jurisdiction FR
Data Source google_patents
Last Synchronized 2026-11-01 19:34
CPC Classifications
H; H10; H10W; H10W42/00; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

DE2656489A1 Cited
EP0079775A2 Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag