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FR2499732A2 Expired / Lapsed FR ⏱️ 0.0 years remaining

Nested loop processor for sequential computer program - uses memories to hold loop data, loop count, and return addresses to command table to dispatch to loop processing system

Assignee: Individual
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Filing: 1980-12-31
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Granted: —
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Expires: 2000-12-31
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Abstract

Abstract The processor uses stored values of start and finish of loops to facilitate processing of nested program sectors, and also holds target addresses for entry to and exit from the loops. The information required for program transfers is then immediately accessible rather than obtained after a lengthy sequential scan. The controlling processor is coupled to the loop controller which has memories holding loop count requirements, and counter registers which count the executed loops. The restart of each loop is held in another memory which redirects the program to the command table from which the processor obtains the next instruction.

Inventors

  • 👤 Bertrand De Rivals-Mazeres
  • 👤 Jacques Brocard
  • 👤 Jacques Vidalin

Bibliographic Details

Application Number —
Jurisdiction FR
Data Source google_patents
Last Synchronized 2026-11-01 12:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/325; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90348

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

FR2289962A1 Cited
FR2330075A2 Cited
FR2421422A1 Cited
US4241402A Cited

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