Patent EP1209747A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP1209747A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor memory element

Assignee: Hitachi Ltd
•
Filing: 1996-01-26
•
Granted: —
•
Expires: 2016-01-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor memory element comprises a semiconductor film (1) formed on a substrate, two low-resistance regions (102, 103) coupled with end portions of the semiconductor film, and a control electrode (104) for applying an electric field to the semiconductor film. The element is formed as a one-transistor memory cell in which information is stored by a change in threshold voltage due to charge carrier trapping. The semiconductor film (1) includes a plurality of strips (101) interconnecting the low-resistance regions (102, 103) and being controlled by a common control electrode (104). The control electrode (104) covers the entirety of the semiconductor film strips (101). A second control electrode may be provided for applying an electric field to the semiconductor film.

Inventors

  • 👤 Tomoyuki Ishii
  • 👤 Kazuo Yano
  • 👤 Koichi Seki
  • 👤 Toshiyuki Mine
  • 👤 Takashi Kobayashi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 08:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10B; H10B69/00; H10D30/681; H10D30/683; H10D48/00; H10D48/30; H10D48/32; H10D48/366; H10D86/00; H10D86/201; Y; Y10; Y10S; Y10S438/00; Y10S438/962

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 107 words
A semiconductor memory element comprising: a semiconductor film (1) formed on a substrate, two low-resistance regions (102, 103) coupled with end portions of said semiconductor film, a control electrode (104) for applying an electric field to said semiconductor film, the element being formed as a one-transistor memory cell in which information is stored by a change in threshold voltage due to charge carrier trapping, characterised in that said semiconductor film (1) includes a plurality of strips (101) interconnecting said low-resistance regions (102, 103) and being controlled by a common control electrode (104), said control electrode (104) covering the entirety of said semiconductor film strips (101). (Fig. 16)
Claim 2
Dependent Claim 107 words
A semiconductor memory element comprising: a semiconductor film (1) formed on a substrate, two low-resistance regions (102, 103) coupled with end portions of said semiconductor film, a control electrode (104) for applying an electric field to said semiconductor film, the element being formed as a one-transistor memory cell in which information is stored by a change in threshold voltage due to charge carrier trapping, characterised in that said semiconductor film (1) includes a plurality of strips (101) interconnecting said low-resistance regions (102, 103) and being controlled by a common control electrode (104), said control electrode (104) covering the entirety of said semiconductor film strips (101). (Fig. 16)
Claim 3
Dependent Claim 25 words
The memory element of claim 1, further comprising a second control electrode (120) for applying an electric field to said semiconductor film (117). (Fig. 18)
Claim 4
Dependent Claim 111 words
A semiconductor memory element comprising: a semiconductor film (1; 117) formed on a substrate, two low-resistance regions (2, 3; 102, 103) coupled with end portions of said semiconductor film (1; 117), a first control electrode (4) for applying an electric field to said semiconductor film (1; 117), the element being formed as a one-transistor memory cell in which information is stored by a change in threshold voltage due to charge carrier trapping, characterised in    that the first control electrode (4) covers the entirety of said semiconductor film (1; 117) and that a second control electrode (120) is provided for applying an electric field to said semiconductor film. ( Fig. 18 )
Claim 5
Dependent Claim 111 words
A semiconductor memory element comprising: a semiconductor film (1; 117) formed on a substrate, two low-resistance regions (2, 3; 102, 103) coupled with end portions of said semiconductor film (1; 117), a first control electrode (4) for applying an electric field to said semiconductor film (1; 117), the element being formed as a one-transistor memory cell in which information is stored by a change in threshold voltage due to charge carrier trapping, characterised in    that the first control electrode (4) covers the entirety of said semiconductor film (1; 117) and that a second control electrode (120) is provided for applying an electric field to said semiconductor film. ( Fig. 18 )
Claim 6
Dependent Claim 33 words
The memory element of claim 3, wherein said semiconductor film includes a plurality of strips (101) interconnecting said low-resistance regions (102, 103) and being controlled by a common control electrode (104). (Fig. 16)
Claim 7
Dependent Claim 25 words
The memory element of claim 1, wherein said semiconductor film (1; 117) is made of polycrystalline silicon having a thickness of 5 nm or less.
Claim 8
Dependent Claim 21 words
The memory element of any preceding claim, wherein said low-resistance regions (2, 3; 102, 103) are formed over an insulator (6).
Claim 9
Dependent Claim 25 words
The memory element of any preceding claim, wherein said low-resistance regions (2, 3; 102, 103) are connected with a wiring line of an another layer.
Claim 10
Dependent Claim 22 words
The memory element of any preceding claim, wherein said semiconductor film has a laterally projecting portion extending parallel to the substrate surface.
Claim 11
Dependent Claim 19 words
The memory element of any preceding claim, wherein said semiconductor film (1; 117) is formed over an insulator (6).
Claim 12
Dependent Claim 16 words
The memory element of claim 5 or 8, wherein said insulator (6) is made of nitride.
Claim 13
Dependent Claim 23 words
The memory element of any preceding claim, wherein the memory region is located in said semiconductor film (1; 117) as a low-potential region.
Claim 14
Dependent Claim 23 words
The memory element of any one of claims 1 to 10, wherein the memory region is separate from said semiconductor film (1; 117).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag