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EP1145128A2
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A memory address translation system and method for a memory having multiple storage units
Assignee: Unisys Corp
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Filing: 1999-12-17
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Granted: —
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Expires: 2019-12-17
Abstract
Abstract A memory address translation system and method for use in a computer system having one or more processors coupled to supply (i.e., issue) addresses to a main memory, wherein the main memory includes multiple Memory Storage Units (MSUs), and wherein the multiple MSUs are divided into multiple groups of MSUs. An address issued by a processor is first mapped to a selected one of the multiple groups of MSUs according to a first mapping function, and then the address is further mapped to a selected one of the MSUs that is included in the selected group.
Inventors
- 👤 Robert C. Gulick
- 👤 Douglas E. Morrissey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 16:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0692; G06F12/0223; G06F12/0284
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