Patent EP1137188A2 successfully refreshed from Google Patents.
EP1137188A2
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Digital phase lock loop
Assignee: STMicroelectronics lnc USA
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Filing: 2001-03-07
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Granted: —
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Expires: 2021-03-07
Abstract
Abstract A system includes an all digital circuit implementation and standard cell construction of PLL (108) with a digital frequency synthesizer and a digital phase detector (224). The synthesizer includes a digital DLL (202) including a plurality of delay chains, each including at least one digitally programmable delay element to achieve a phase lock with an input reference signal. The synthesizer also comprises a non-glitching MUX (206) electrically coupled to the digital DLL (202) for selecting a tap output from one of the delay elements to select at least one pulse glitch-free from the selected output tap, and a phase accumulator (208) electrically coupled to the MUX (206) for precisely dividing a timing period of the input reference signal and selecting a tap output from one delay element to select at least one pulse at a precise point in the timing period from the output tap. The phase detector (224), is electrically coupled to the synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal. <IMAGE>
Inventors
- 👤 William D. Elliot
- 👤 Charles Neugebauer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:15
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/003; G09G5/006; G09G5/008; H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H03K5/13; H03K5/131; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0818; H03L7/085; H03L7/089; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03L2207/00; H03L2207/50
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
196 words
A digital phase lock loop comprising: a digital frequency synthesizer comprising: a digital DLL including a plurality of delay chains, each of the delay chains
including at least one digitally programmable delay element for configuring the plurality
of delay chains to achieve a phase lock with an input reference signal; a non-glitching MUX electrically coupled to the digital DLL for selecting a
tap output from one of the at least one digitally programmable delay element to select at
least one pulse glitch-free from the selected output tap; and a phase accumulator electrically coupled to the non-glitching MUX for
precisely dividing a timing period of the input reference signal and for selecting a tap
output from one of the at least one digitally programmable delay element to select at
least one pulse at a precise point in the timing period from the output tap; and a digital phase detector, electrically coupled to the digital frequency synthesizer
to compare an edge of the input reference signal to an edge of a synthesized signal to
provide a digital code information representing a phase error between the edge of the
input reference signal and the edge of the synthesized signal.
Claim 2
Independent Claim
223 words
A system comprising: a controller; a first input for receiving an input reference signal with a first edge; digital phase lock loop, electrically coupled to the controller and to the first input,
comprising: a digital frequency synthesizer comprising: a digital DLL including a plurality of delay chains, each of the delay
chains including at least one digitally programmable delay element for configuring the
plurality of delay chains to achieve a phase lock with an input reference signal; a non-glitching MUX electrically coupled to the digital DLL for
selecting a tap output from one of the at least one digitally programmable delay element
to select at least one pulse glitch-free from the selected output tap; and a phase accumulator electrically coupled to the non-glitching MUX
for precisely dividing a timing period of the input reference signal and for selecting a tap
output from one of the at least one digitally programmable delay element to select at
least one pulse at a precise point in the timing period from the output tap; and a digital phase detector, electrically coupled to the digital frequency synthesizer
to compare an edge of the input reference signal to an edge of a synthesized signal to
provide a digital code information representing a phase error between the edge of the
input reference signal and the edge of the synthesized signal.
Claim 3
Dependent Claim
258 words
A flat panel monitor comprising: a controller for controlling functions of the flat panel monitor; a display for displaying information; a video interface including a first input for receiving a first signal with a first edge;
and a digital PLL, electrically coupled to the video interface, the controller, and the
display, for generating, at a second input, a second signal with a second edge, the digital PLL including: a digital frequency synthesizer comprising: a digital DLL including a plurality of delay chains, each of the delay
chains including at least one digitally programmable delay element for configuring the
plurality of delay chains to achieve a phase lock with an input reference signal; a non-glitching MUX electrically coupled to the digital DLL for
selecting a tap output from one of the at least one digitally programmable delay element
to select at least one pulse glitch-free from the selected output tap; and a phase accumulator electrically coupled to the non-glitching MUX
for precisely dividing a timing period of the input reference signal and for selecting a tap
output from one of the at least one digitally programmable delay element to select at
least one pulse at a precise point in the timing period from the output tap; and a digital phase detector, electrically coupled to the digital frequency
synthesizer to compare an edge of the input reference signal to an edge of a
synthesized signal to provide a digital code information representing a phase error
between the edge of the input reference signal and the edge of the synthesized signal.
Claim 4
Dependent Claim
23 words
Apparatus according to any one of claims 1, 2 or 3, wherein the selected
at least one pulse corresponds to the synthesized signal.
Claim 5
Dependent Claim
75 words
Apparatus according to any one of claims 1, 2 or 3, further comprising: a digital controller electrically coupled to the digital phase detector and the
digital frequency synthesizer; and a memory electrically coupled to the controller, and including instructions
for the controller to control the digital frequency synthesizer to generate a synthesized signal;
and use the digital code to adjust the phase of the synthesized signal to match
a phase of the input reference signal.
Claim 6
Dependent Claim
25 words
Apparatus of claim 5, wherein the memory further includes instructions for
the controller to perform a digital loop filter function on the digital code
information.
Claim 7
Dependent Claim
17 words
The apparatus of claim 6, wherein the digital loop filter function comprises
a low pass filter function.
Claim 8
Dependent Claim
34 words
Apparatus according to any one of claims 1, 2 or 3, wherein the digital
DLL, the non-glitching MUX, the phase accumulator, and digital phase detector,
are all constructed using an all digital circuit implementation.
Claim 9
Dependent Claim
19 words
The apparatus of claim 8, wherein the all digital circuit implementation
comprises standard cell construction for an integrated circuit.
Claim 10
Dependent Claim
31 words
Apparatus according to any one of claims 1,2, or 3, wherein the digital
DLL, the non-glitching MUX, the phase accumulator, and the digital phase
detector, are incorporated into an integrated circuit.
Claim 11
Dependent Claim
33 words
Apparatus according to any one of claims 1, 2 or 3, wherein the input
reference signal is a reference horizontal sync signal and the synthesized
horizontal sync signal for driving a display monitor.
References Cited (Backward Citations)
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