Patent EP1032099A2 successfully refreshed from Google Patents.
EP1032099A2
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Semiconductor device and method of fabricating the same
Assignee: Panasonic Corp
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Filing: 2000-02-25
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Granted: —
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Expires: 2020-02-25
Abstract
Abstract A semiconductor device comprises a substrate having a first thermal expansion coefficient T1, a strain reducing layer formed on the substrate and having a second thermal expansion coefficient T2, and a semiconductor layer formed on the strain reducing layer, having a third thermal expansion coefficient T3, and made of a nitride compound represented by Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦ 1). The second thermal expansion coefficient T2 is lower than the first thermal expansion coefficient T1. The third thermal expansion coefficient T3 is lower than the first thermal expansion coefficient T1 and higher than the second thermal expansion coefficient T2.
Inventors
- 👤 Masahiro Ishida
- 👤 Masaaki Yuri
- 👤 Osamu Imafuji
- 👤 Shinji Nakamura
- 👤 Kenji Orita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:54
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/01; H10H20/011; H10H20/013; H10H20/0133; H10H20/01335; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2921; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3214; H10P14/3216; H10P14/3242; H10P14/3244; H10P14/3248; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3416; H01; H01S; H01S5/00; H01S5/30; H01S5/32; H01S5/323; H01S5/32308; H01S5/32341; H10H20/018
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
117 words
A semiconductor device comprising: a substrate having a first thermal expansion coefficient
T1; a strain reducing layer having a second thermal expansion
coefficient T2, the strain reducing layer being formed on the
substrate; and a semiconductor layer having a third thermal expansion
coefficient T3, the semiconductor layer being formed on the strain
reducing layer and made of a nitride compound represented by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦1), the second thermal expansion coefficient T2 being lower
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being lower than
the first thermal expansion coefficient T1 and higher than the
second thermal expansion coefficient T2.
Claim 2
Dependent Claim
56 words
The semiconductor device of claim 1, wherein a ratio T1/T3 of the first thermal expansion coefficient
T1 to the third thermal expansion coefficient T3 is lower than
a ratio T3/T2 of the third thermal expansion coefficient T3 to
the second thermal expansion coefficient T2 and the substrate is larger in thickness than the strain
reducing layer.
Claim 3
Dependent Claim
56 words
The semiconductor device of claim 1, wherein a ratio T1/T3 of the first thermal expansion coefficient
T1 to the third thermal expansion coefficient T3 is higher than
a ratio T3/T2 of the third thermal expansion coefficient T3 to
the second thermal expansion coefficient T2 and the substrate is smaller in thickness than the strain
reducing layer.
Claim 4
Dependent Claim
22 words
The semiconductor device of claim 1, wherein the
substrate is made of sapphire and the strain reducing layer is
made of silicon.
Claim 5
Dependent Claim
30 words
The semiconductor device of claim 4, wherein the
substrate has a main surface having a (0001) plane and the strain
reducing layer has a growth interface having a (111) plane.
Claim 6
Dependent Claim
117 words
A semiconductor device comprising: a substrate having a first thermal expansion coefficient
T1; a strain reducing layer having a second thermal expansion
coefficient T2, the strain reducing layer being formed on the
substrate; and a semiconductor layer having a third thermal expansion
coefficient T3, the semiconductor layer being formed on the strain
reducing layer and made of a nitride compound represented by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦1), the second thermal expansion coefficient T2 being higher
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being higher
than the first thermal expansion coefficient T1 and lower than
the second thermal expansion coefficient T2.
Claim 7
Dependent Claim
56 words
The semiconductor device of claim 6, wherein a ratio T3/T1 of the third thermal expansion coefficient
T3 to the first thermal expansion coefficient T1 is lower than
a ratio T2/T3 of the second thermal expansion coefficient T2 to
the third thermal expansion coefficient T3 and the substrate is larger in thickness than the strain
reducing layer.
Claim 8
Dependent Claim
56 words
The semiconductor device of claim 6, wherein a ratio T3/T1 of the third thermal expansion coefficient
T3 to the first thermal expansion coefficient T1 is higher than
a ratio T2/T3 of the second thermal expansion coefficient T2 to
the third thermal expansion coefficient T3 and the substrate is smaller in thickness than the strain
reducing layer.
Claim 9
Independent Claim
118 words
A method of fabricating a semiconductor device, the
method comprising the steps of: forming a strain reducing layer having a second thermal
expansion coefficient T2 on a substrate having a first thermal
expansion coefficient T1; and forming a semiconductor layer having a third thermal
expansion coefficient T3 on the strain reducing layer, the
semiconductor layer being made of a nitride compound represented
by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦1), the second thermal expansion coefficient T2 being lower
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being lower than
the first thermal expansion coefficient T1 and higher than the
second thermal expansion coefficient T2.
Claim 10
Dependent Claim
131 words
The method of claim 9, wherein the step of forming the
strain reducing layer includes the step of forming, when a ratio
T1/T3 of the first thermal expansion coefficient T1 to the third
thermal expansion coefficient T3 is lower than a ratio T3/T2 of
the third thermal expansion coefficient T3 to the second thermal
expansion coefficient T2, the strain reducing layer such that the
strain reducing layer is smaller in thickness than the substrate
and forming, when the ratio T1/T3 of the first thermal expansion
coefficient T1 to the third thermal expansion coefficient T3 is
higher than the ratio T3/T2 of the third thermal expansion
coefficient T3 to the second thermal expansion coefficient T2,
the strain reducing layer such that the strain reducing layer is
larger in thickness than the substrate.
Claim 11
Dependent Claim
21 words
The method of claim 9, wherein the substrate is made
of sapphire and the strain reducing layer is made of silicon.
Claim 12
Dependent Claim
42 words
The method of claim 11, wherein the step of forming the
strain reducing layer includes the step of forming the strain
reducing layer having a growth interface having a (111) plane on
the substrate having a main surface having a (0001) plane.
Claim 13
Independent Claim
118 words
A method of fabricating a semiconductor device, the
method comprising the steps of: forming a strain reducing layer having a second thermal
expansion coefficient T2 on a substrate having a first thermal
expansion coefficient T1; and forming a semiconductor layer having a third thermal
expansion coefficient T3 on the strain reducing layer, the
semiconductor layer being made of a nitride compound represented
by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦1), the second thermal expansion coefficient T2 being higher
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being higher
than the first thermal expansion coefficient T1 and lower than
the second thermal expansion coefficient T2.
Claim 14
Dependent Claim
131 words
The method of claim 13, wherein the step of forming the
strain reducing layer includes the step of forming, when a ratio
T3/T1 of the third thermal expansion coefficient T3 to the first
thermal expansion coefficient T1 is lower than a ratio T2/T3 of
the second thermal expansion coefficient T2 to the third thermal
expansion coefficient T3, the strain reducing layer such that the
strain reducing layer is smaller in thickness than the substrate
and forming, when the ratio T3/T1 of the third thermal expansion
coefficient T3 to the first thermal expansion coefficient T1 is
higher than the ratio T2/T3 of the second thermal expansion
coefficient T2 to the third thermal expansion coefficient T3, the
strain reducing layer such that the strain reducing layer is
larger in thickness than the substrate.
Claim 15
Independent Claim
149 words
A method of fabricating a semiconductor device, the
method comprising the steps of: forming a strain reducing layer having a second thermal
expansion coefficient T2 on a substrate having a first thermal
expansion coefficient T1; forming a semiconductor layer having a third thermal
expansion coefficient T3 on the strain reducing layer, the
semiconductor layer being made of a nitride compound represented
by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦1); and separating the nitride compound semiconductor layer from
a multilayer structure composed of the substrate and the strain
reducing layer to form a semiconductor substrate composed of the
nitride compound semiconductor layer, the second thermal expansion coefficient T2 being lower
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being lower than
the first thermal expansion coefficient T1 and higher than the
second thermal expansion coefficient T2.
Claim 16
Dependent Claim
131 words
The method of claim 15, wherein the step of forming the
strain reducing layer includes the step of forming, when a ratio
T1/T3 of the first thermal expansion coefficient T1 to the third
thermal expansion coefficient T3 is lower than a ratio T3/T2 of
the third thermal expansion coefficient T3 to the second thermal
expansion coefficient T2, the strain reducing layer such that the
strain reducing layer is smaller in thickness than the substrate
and forming, when the ratio T1/T3 of the first thermal expansion
coefficient T1 to the third thermal expansion coefficient T3 is
higher than the ratio T3/T2 of the third thermal expansion
coefficient T3 to the second thermal expansion coefficient T2,
the strain reducing layer such that the strain reducing layer is
larger in thickness than the substrate.
Claim 17
Dependent Claim
21 words
The method of claim 15, wherein the substrate is made
of sapphire and the strain reducing layer is made of silicon.
Claim 18
Dependent Claim
42 words
The method of claim 17, wherein the step of forming the
strain reducing layer includes the step of forming the strain
reducing layer having a growth interface having a (111) plane on
the substrate having a main surface having a (0001) plane.
Claim 19
Dependent Claim
30 words
The method of claim 17, wherein the step of forming the
semiconductor substrate includes the step of removing the strain
reducing layer by using a solution containing a hydrofluoric acid.
Claim 20
Independent Claim
150 words
A method of fabricating a semiconductor device, the
method comprising the steps of: forming a strain reducing layer having a second thermal
expansion coefficient T2 on a substrate having a first thermal
expansion coefficient T1; forming a semiconductor layer having a third thermal
expansion coefficient T3 on the strain reducing layer, the
semiconductor layer being made of a nitride compound represented
by
Al y Ga 1-y-z In z N (0 ≦ y ≦ 1, 0 ≦ z ≦ 1); and separating the nitride compound semiconductor layer from
a multilayer structure composed of the substrate and the strain
reducing layer to form a semiconductor substrate composed of the
nitride compound semiconductor layer, the second thermal expansion coefficient T2 being higher
than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being higher
than the first thermal expansion coefficient T1 and lower than
the second thermal expansion coefficient T2.
Claim 21
Dependent Claim
131 words
The method of claim 20, wherein the step of forming the
strain reducing layer includes the step of forming, when a ratio
T3/T1 of the third thermal expansion coefficient T3 to the first
thermal expansion coefficient T1 is lower than a ratio T2/T3 of
the second thermal expansion coefficient T2 to the third thermal
expansion coefficient T3, the strain reducing layer such that the
strain reducing layer is smaller in thickness than the substrate
and forming, when the ratio T3/T1 of the third thermal expansion
coefficient T3 to the first thermal expansion coefficient T1 is
higher than the ratio T2/T3 of the second thermal expansion
coefficient T2 to the third thermal expansion coefficient T3, the
strain reducing layer such that the strain reducing layer is
larger in thickness than the substrate.
References Cited (Backward Citations)
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