Patent EP0964517A2 successfully refreshed from Google Patents.
EP0964517A2
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Delay locked loop
Assignee: Infineon Technologies AG
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Filing: 1999-06-09
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Granted: —
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Expires: 2019-06-09
Abstract
Abstract A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.
Inventors
- 👤 Jean-Marc Dortu
- 👤 Albert M. Chu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
106 words
A clock to data latency compensation circuit for a system associated
with at least one integrated circuit comprising: a receiver, said receiver being operable to receive a system clock
signal and output a first clock signal and a second clock signal ; delay circuitry being operable to receive said first and second clock
signais and output time shifted clock signals corresponding to said first
and second clock signals; and a phase comparator operable to control said delay line circuitry in
connection with the detection of phase shift between said first and second
clock signals and said time-shifted signals corresponding to said first and
second clock signals.
Claim 2
Dependent Claim
39 words
A clock to data latency compensation circuit as recited in claim 1
which further comprises logic circuitry having an output and at least one
input, said logic circuitry being operable to receive said time-shifted
signals from said delay circuitry.
Claim 3
Dependent Claim
60 words
A clock to data latency compensation circuit as recited in claim 2
which further comprises a driver having a first input connected to the
output of said logic circuitry and a second input being operable to receive
data, said driver being operable to output said data such that it is
synchronized with rising and falling edges of said system clock.
Claim 4
Dependent Claim
22 words
A clock to data latency compensation circuit as recited in claim 1
wherein said receiver comprises at least one monostable multivibrator
circuit.
Claim 5
Dependent Claim
43 words
A clock to data latency compensation circuit as recited in claim 1
wherein said delay circuit comprises circuitry consisting of the following: variable passive impedance circuitry; variable active impedance
circuitry; microcontroller circuitry; microcomputer circuitry; digital signal
processing circuitry ; or a combination thereof.
Claim 6
Dependent Claim
20 words
A synchronous random access memory integrated circuit chip which
includes the clock latency compensation circuit as recited in claim 1.
Claim 7
Dependent Claim
57 words
A synchronous random access memory system including a plurality
of memory integrated circuit chips as recited in claim 6, each
compensation circuit including on each said integrated circuit chip being
operable to generate a data strobe signal, said memory system including a
controller used in connection with synchronizing data coming from said
plurality- of integrated circuit chips.
Claim 8
Independent Claim
98 words
A method of clock latency compensation for a system comprising: generating a first clock signal and a second clock signal in response
to rising and falling edges of a system clock; processing and propagating said first and second clocks signals
through circuitry operable to adjustably alter the propagation time of said
signals therethrough; and controlling the adjustment of said propagation time in response to a
comparison of the phase of at least one of said first and second clock
signals prior to and after propagation through and processing by said
circuitry operable to adjustably alter said propagation time.
Claim 9
Dependent Claim
56 words
A method as recited in claim 8 which further comprises: further processing said first and second signals using Boolean logic,
after propagation through said circuitry operable to adjustably alter said
propagation time, and using said Boolean logic processed first and second
signals to synchronize data with said rising and falling edges of said
system clock signal.
References Cited (Backward Citations)
No citation records indexed.
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