Patent EP0962856A2 successfully refreshed from Google Patents.
EP0962856A2
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EP
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A dual-mode VLIW architecture with software-controlled parallelism
Assignee: Texas Instruments Inc
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Filing: 1999-05-28
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Granted: —
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Expires: 2019-05-28
Abstract
Abstract This invention is a very long instruction word data processor (200) including plural data registers (140A, 140B), plural functional units (130A, 130B) and plural program counters (110A, 110B) and is selectively operable in either a first or second mode. In the first mode, the data processor executes a single instruction stream. In the second mode, the data processor executes two independent program instruction streams simultaneously. In the second mode the data processor may respond to two instruction streams accessing only corresponding halves of the data registers and function units. Alternatively, the data processor may respond to a first instruction stream including instructions referencing the whole data processor employing A side function units by alternatively dispatching (1) instructions referencing the A side data registers and the A side function units and (2) instructions referencing the B side data registers and the B side function units. In the first mode, the data processor fetches N bits of instructions each cycle. In the second mode the data processor may fetch N bits of instructions for alternate program counters on alternate cycles or fetches N/2 bits of each of the first and second program counters. The data processor includes interrupt steering and masking control logic (125) allowing instructions to control whether the first instruction stream or the second instruction stream receives interrupts.
Inventors
- 👤 David H. Bartley
- 👤 Jonathan H. Shiell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/3891; G06F9/30003; G06F9/30076; G06F9/3009; G06F9/3802; G06F9/3836; G06F9/3851; G06F9/3853
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
129 words
A very long instruction word data processor
comprising: plural data registers; plural functional units; and plural program counters; said data processor being selectively operable according to a first mode in which program instructions are
executed by selected ones of the data registers and selected
ones of the functional units, under the control of a
predetermined one of the program counters; and a second mode in which a first program counter
controls execution of program instructions using a first group
of data registers and a first group of functional units, and a
second program counter controls execution of program
instructions using a second group of data registers disjoint
from said first group of data registers and a second group of
functional units disjoint from said first group of functional
units.
Claim 2
Dependent Claim
129 words
The very long instruction word data processor of claim
1, wherein: the plural data registers consists of an A side of one half
of the plural data registers and a B side of a disjoint set of
one half of the plural data registers; the plural function units consists of an A side of one half
of the plural function units and a B side of a disjoint set of
one half of the plural function units; the first program counter is associated with the A side
data registers and the A side function units; the second program counter is associated with the B side
data registers and the B side function units; whereby in the second mode the data processor can processes
two independent program instruction streams simultaneously.
Claim 3
Dependent Claim
114 words
The very long instruction word data processor of claim
2, further comprising: plural control registers, at least one control register
having an A side component and a B side component; and wherein in the first mode operation of data registers and
function units is controlled by the A side component of the at
least one control register, and in the second mode the operation of A side data
registers and A side function units is controlled by the A side
component of the at least one control register and the operation
of B side data registers and B side function units controlled by
the B side component of the at least one control register.
Claim 4
Dependent Claim
113 words
The very long instruction word data processor in claim
2, wherein the data processor: is responsive in the second mode to a first instruction
stream including only instructions referencing one half of the
plural data processors and one half of the function units
controlled by the first program counter and executed employing
the A side data registers and the A side function units, and is responsive in the second mode to a second instruction
stream including only instructions referencing one half of the
plural data processors and one half of the function units
controlled by the second program counter and executed employing
the B side data registers and the B side function units.
Claim 5
Dependent Claim
131 words
The very long instruction word data processor in claim
2, wherein the data processor: is responsive in the second mode to a first instruction
stream including instructions referencing any of the plural data
registers and any of the plural function units controlled by the
first program counter and executed employing the A side function
units by alternatively dispatching (1) instructions referencing
the A side data registers and the A side function units and (2)
instructions referencing the B side data registers and the B
side function units, and is responsive in the second mode to a second instruction
stream including only instructions referencing one half of the
plural data processors and one half of the function units
controlled by the second program counter and executed employing
the B side function units.
Claim 6
Dependent Claim
91 words
The very long instruction word data processor in claim
5, further comprising: a program memory storing instructions for control of the
data processor; and wherein in the first mode the data processor fetches N bits
of instructions from the program memory each cycle corresponding
to the first program counter; wherein in the second mode the data processor on alternate
cycles fetches N bits of instructions from the program memory
corresponding to the first program counter, and fetches N bits of instructions from the program memory
corresponding to the second program counter.
Claim 7
Dependent Claim
88 words
The very long instruction word data processor in claim
5, further comprising: a program memory storing instructions for control of the
data processor; and wherein in the first mode the data processor fetches N bits
of instructions from the program memory each cycle corresponding
to the first program counter; wherein in the second mode the data processor fetches N/2
bits of instructions from the program memory corresponding to
the first program counter, and fetches N/2 bits of instructions
from the program memory corresponding to the second program
counter.
Claim 8
Dependent Claim
33 words
The very long instruction word data processor in claim
2, wherein: switching between the first mode and the second mode and
between the second mode and the first mode is controlled by
instructions.
Claim 9
Dependent Claim
74 words
The very long instruction word data processor in claim
8, wherein: the data processor switches between the first mode and the
second mode upon storing a first set of bits in predetermined
locations within a first control register; and the data processor switches between the second mode and the
first mode upon storing a first set of bits difference from the
first set of bits in the predetermined locations within the
first control register.
Claim 10
Dependent Claim
48 words
The very long instruction word data processor in claim
8, wherein: the data processor switches between the first mode and the
second mode upon execution of a split instruction; and the data processor switches between the second mode and the
first mode upon execution of a join instruction.
Claim 11
Dependent Claim
34 words
The very long instruction word data processor in claim
2, further comprising: interrupt steering and masking control logic allowing
instructions to control whether the first instruction stream or
the second instruction stream receives interrupts.
References Cited (Backward Citations)
No citation records indexed.
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