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EP0933926A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

DMA controller

Assignee: STMicroelectronics Ltd Great Britain
•
Filing: 1999-01-29
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Granted: —
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Expires: 2019-01-29
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Abstract

Abstract There is disclosed a controller for controlling direct memory access. Such controller is particularly applicable when applied to a transport interface in the receiver of a digital set-top-box for television systems. Storage means stores the base and top addresses of a circular buffer in a memory to which received data is to be forwarded and stored, and a write pointer for such buffer is also stored in the storage means. Addressing circuitry generates the address to which the receive data is to be written in dependence on the stored base and top addresses and the write pointer. Output circuitry writes the data into the circular buffer at the location identified by the generated address.

Inventors

  • 👤 Andrew Maccormack

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 15:43
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/434

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 91 words
A memory controller comprising: input circuitry for receiving data to be stored in the memory; storage means for storing the base and top addresses of a circular buffer in the memory to which the received data is to be stored, and for storing a write pointer for the buffer; addressing circuitry for generating the address to which the received data is to be written in dependence on the stored base and top address and write pointer; and output circuitry for writing the data into the circular buffer at the generated address.
Claim 2
Dependent Claim 19 words
The memory controller of claim 1, in which the storage means further stores a read pointer for the buffer.
Claim 3
Dependent Claim 78 words
The memory controller of claim 1 or claim 2, in which the storage means further stores the base and top addresses of a circular buffer defined in the memory and associated with a peripheral device together with read and write pointers for said buffer, the memory controller further comprising a control circuit responsive to said read and write pointers not being equal to control the output circuitry to write data from said circular buffer to the peripheral device.
Claim 4
Dependent Claim 36 words
The memory of claim 3, in which the storage means stores a plurality of top and base addresses, and read and write pointers, of a plurality of circular buffers associated with a plurality of peripheral devices.
Claim 5
Dependent Claim 53 words
A receiver for demultiplexing a digital data stream comprising: input means for receiving the digital data stream; a control means for demultiplexing the received digital data stream and generating demultiplexed data; and a memory controller according to any one of claims 1 to 4, for controlling storage in memory of the demultiplexed data.
Claim 6
Dependent Claim 15 words
The receiver of claim 5, in which the digital data stream comprises MPEG-2 encoded data.
Claim 7
Dependent Claim 21 words
The receiver of claim 6 when dependent on claims 5 and 3, in which the peripheral device is an MPEG-2 decoder.
Claim 8
Independent Claim 85 words
A method of controlling storage of data in a memory comprising: receiving data to be stored in the memory; storing base and top addresses of a circular buffer in memory to which the received data is to be transferred, and storing a write pointer for the buffer; generating an address to which the received data is to be written in dependence on the stored base and top addresses and the stored write pointer; and writing the data into the circular buffer at the generated address.

References Cited (Backward Citations)

US5361372A Cited
US5446839A Cited
EP0735776A2 Cited
US5602920A Cited
EP0785675A2 Cited

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