EP0930709A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit for producing pulse signals with a desired duty cycle
Assignee: NEC Corp
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Filing: 1999-01-18
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Granted: —
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Expires: 2019-01-18
Abstract
Abstract An integrated circuit has a first circuit which receives an input signal and outputs a first output signal, wherein the first output signal is produced by changing the pulse width of the input signal, a second circuit which receives the first output signal and outputs a second output signal, wherein the second output signal is produced by delaying the first output signal and a control circuit. The control circuit has a first control circuit which receives the first and second output signals and controls the first circuit based on the first and second output signals and a second control circuit which receives the first and second output signals and controls the second circuit based on the first and second output signals.
Inventors
- 👤 Hiroshi Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:10
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
113 words
An integrated circuit comprising: a first circuit which receives an input signal and outputs a first output signal,
wherein said first output signal is produced by changing the pulse width of said input
signal; a second circuit which receives said first output signal and outputs a second
output signal wherein said second output signal is produced by delaying said first
output signal; a first control circuit which receives said first and second output signals and
controls said first circuit based on said first and second output signals; and a second control circuit which receives said first and second output signals and
controls said second circuit based on said first and second output signals.
Claim 2
Dependent Claim
30 words
The integrated circuit as claimed in claim 1, wherein said first control circuit
controls said first circuit based on times when levels of said first and second output
signals change.
Claim 3
Dependent Claim
31 words
The circuit as claimed in claim 1 or 2, wherein said second control circuit
controls said second circuit based on times when levels of said first and second output
signals change.
Claim 4
Dependent Claim
37 words
The circuit as claimed in claim 1,2 or 3, wherein said first control circuit
controls said first circuit so that the level of said first output signal falls when the level of
said second output signal rises.
Claim 5
Dependent Claim
39 words
The circuit as claimed in claim 1, 2, 3 or 4, wherein said second control circuit
controls said second circuit so that the level of said first output signal rises when the
level of said second output signal falls.
Claim 6
Dependent Claim
110 words
An integrated circuit comprising: a first circuit which receives an input signal, and outputs a first output signal
which is increased in proportion to a high level width of said input signal to a low level
width of said input signal when said high level width is less than the low level width or
in proportion to the low level width of said input signal to the high level width of said
input signal when said low level width is less than the high level width; and a second circuit which receives said first output signal and outputs a second
output signal which is produced by delaying said output signal.
Claim 7
Dependent Claim
44 words
The integrated circuit as claimed in claim 6 , further comprising: a first control
circuit which receives said first output signal and a second output signal, and controls
said first circuit based on the phases of said first output signal and second output
signal.
Claim 8
Dependent Claim
44 words
The circuit as claimed in claim 6 or 7, further comprising: a second
control circuit which receives said first output signal and a second output signal, and
controls said second circuit based on the phases of said first output signal and second
output signal.
Claim 9
Dependent Claim
68 words
The circuit as claimed in any one of claims 1 to 8, wherein said first
control circuit has a first terminal which receives a falling edge of said first output signal and a second
terminal which receives a rising edge of said second output signal, and reduces a
phase difference between said falling edge of said first output signal and said rising
edge of said second output signal.
Claim 10
Dependent Claim
68 words
The circuit as claimed in any one of claims 1 to 9, wherein said
second control circuit has a first terminal which receives a rising edge of said first output signal and a second
terminal which receives a falling edge of said second output signal, and reduces a
phase difference between said rising edge of said first output signal and said falling
edge of said second output signal.
Claim 11
Dependent Claim
50 words
The circuit as claimed in any one of claims 1 to 10, further comprising: a buffer circuit which receives said first output signal and outputs a third output
signal to said second circuit, wherein said third output signal is produced by delaying
said first output signal by said buffer circuit.
Claim 12
Dependent Claim
51 words
The integrated circuit as claimed in claim 11, further comprising: a phase locked loop circuit which receives said input signal and said third output signal,
and outputs a fourth output signal to said first circuit so that a phase of said input signal
adjusts a phase of said third output signal.
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