EP0604126A2
Expired / Lapsed
EP
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Clock signal conditioning circuit
Assignee: Motorola Solutions Inc
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Filing: 1993-12-16
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Granted: —
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Expires: 2013-12-16
Abstract
Abstract A clock signal conditioning circuit (100) for use in a smart card (102) has an input node (112) for receiving an applied clock signal, an output node (126) for producing a conditioned clock signal, a rising/falling edge detector (118) for detecting edges in the received clock signal, a bistable device (122) for forming at the output node a clock signal in response to the edge detector, and a timer (120, 124) for inhibiting switching of the bistable device for a predetermined time (T) following detection by the edge detector of an edge. Such a clock signal conditioning circuit provides a conditioned clock signal which is substantially independent of variations in the duty cycle of the applied clock signal and is substantially immune to glitches in the applied clock signal. <IMAGE>
Inventors
- 👤 Alain Duret
- 👤 Eric Boulian
- 👤 Anil Gercekci
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:08
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K7/00; G06K7/0008; H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
78 words
A clock signal conditioning circuit comprising: an input node for receiving an applied clock signal; an output node for producing thereat a conditioned clock signal; edge detector means for detecting edges in the received clock signal; bistable means for forming at the output node a clock signal in response to the edge detector means; and timer means for inhibiting switching of the bistable means for a predetermined time following detection by the edge detector means of an edge.
Claim 2
Dependent Claim
40 words
A clock signal conditioning circuit according to claim 1 wherein the timer means comprises a monostable pulse generator arranged to be triggered in response to the edge detector means and having an output coupled to disable the edge detector means.
Claim 3
Dependent Claim
38 words
A clock signal conditioning circuit according to claim 1 or 2 wherein the edge detector means comprises an edge detector arranged to detect an edge of a first polarity or a second polarity opposite to the first polarity.
Claim 4
Dependent Claim
107 words
A clock signal conditioning circuit according to claim 1 or 2 wherein: the edge detector means comprises a first edge detector for detecting an edge of a first polarity, and a second edge detector for detecting an edge of a second polarity opposite to the first polarity; and the timer means comprises a first monostable pulse generator arranged to be triggered in response to the first edge detector and having an output coupled to disable the second edge detector, and a second monostable pulse generator arranged to be triggered in response to the second edge detector and having an output coupled to disable the first edge detector.
Claim 5
Dependent Claim
29 words
A clock signal conditioning circuit according to any preceding claim further comprising pulse stretching means coupled to the edge detector means for stretching pulses of the output clock signal.
Claim 6
Dependent Claim
163 words
A clock signal conditioning circuit according to claim 1 or 2 wherein: the edge detector means comprises a first edge detector for detecting an edge of a first polarity, and a second edge detector for detecting an edge of a second polarity opposite to the first polarity; and the timer means comprises: a first monostable pulse generator arranged to be triggered in response to the first edge detector; a second monostable pulse generator arranged to be triggered in response to the second edge detector; first logic means having inputs coupled to the output of the first edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a first input of the bistable means; and second logic means having inputs coupled to the output of the second edge detector and to the outputs of the first and second monostable pulse generators and having an output coupled to a second input of the bistable means.
Claim 7
Dependent Claim
62 words
A clock signal conditioning circuit according to claim 1 or 2 arranged to produce an intermediate signal having a frequency which is an integer multiple of the input clock signal frequency and comprising a frequency divider means coupled to receive the intermediate signal and to produce therefrom a signal having a desired frequency dependent on the frequency of the input clock signal.
Claim 8
Dependent Claim
18 words
A clock signal conditioning circuit according to any preceding claim wherein the bistable means comprises a data latch.
Claim 9
Dependent Claim
19 words
A clock signal conditioning circuit according to any one of claims 1-7 wherein the bistable means comprises a flip-flop.
Claim 10
Dependent Claim
14 words
A smart card containing a clock signal conditioning circuit according to any preceding claim.
References Cited (Backward Citations)
No citation records indexed.
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