Patent US2946129A successfully refreshed from Google Patents.
Patent EP0908945A2 successfully refreshed from Google Patents.
EP0908945A2
Expired / Lapsed
EP
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Dual damascene with self aligned via interconnects
Assignee: Infineon Technologies AG
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Filing: 1998-07-18
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Granted: —
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Expires: 2018-07-18
Abstract
Abstract An improved method of performing a dual damascene etch through a layer stack disposed above a substrate using self aligned vias. The layer stack includes an underlying conductive layer and an insulating layer disposed above the underlying conductive layer. The method includes the following operative steps. A layer of hard resist is deposited upon a top surface of the insulating layer patterned such that a first opening in the hard resist layer is positioned over the underlying device layer. A layer of soft resist is then deposited upon the top surface of the hard resist, the soft resist has a second opening smaller than and aligned to the first opening and the underlying conductive layer. A first trench is then formed in the top surface of the insulating layer positioned over and separated from the underlying device layer by insulating material at a bottom of the trench. The soft resist is then removed without substantially affecting the hard resist. The via is formed by etching through the insulator material at the bottom of the trench down to the underlying device layer.
Inventors
- 👤 Rainer F. Schnabel
- 👤 Klaus Feldner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/087; H10W20/082
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
226 words
A method of performing a dual damascene etch through a layer stack disposed
above a substrate, said layer stack comprising an underlying device layer, an insulating layer
disposed above said underlying device layer, said method comprising: depositing a layer of hard resist above a top surface of said insulating layer, said layer
of hard resist being patterned such that a first opening in said layer of hard resist is positioned
over said underlying device layer, said first opening suitably arranged to define an overlying
metallization; depositing a layer of soft resist above a top surface of said hard resist, said soft resist
being patterned such that a second opening smaller than and aligned to said first opening in
said hard resist is formed, said second opening suitably disposed to form a via interconnect
coupling said overlying metallization layer and said underlying metallization layer; forming a trench in said top surface of said insulating layer using said second opening
as a first mask opening, said trench being positioned over said underlying device layer and
separated therefrom by insulating material at a bottom of said trench; removing said soft resist such that said hard resist is substantially unaffected; and forming a via by etching, using the first opening as a second mask opening, through
said insulating material at bottom of said trench down to said underlying device layer.
Claim 2
Independent Claim
226 words
A method of performing a dual damascene etch through a layer stack disposed
above a substrate, said layer stack comprising an underlying device layer, an insulating layer
disposed above said underlying device layer, said method comprising: depositing a layer of hard resist above a top surface of said insulating layer, said layer
of hard resist being patterned such that a first opening in said layer of hard resist is positioned
over said underlying device layer, said first opening suitably arranged to define an overlying
metallization; depositing a layer of soft resist above a top surface of said hard resist, said soft resist
being patterned such that a second opening smaller than and aligned to said first opening in
said hard resist is formed, said second opening suitably disposed to form a via interconnect
coupling said overlying metallization layer and said underlying metallization layer; forming a trench in said top surface of said insulating layer using said second opening
as a first mask opening, said trench being positioned over said underlying device layer and
separated therefrom by insulating material at a bottom of said trench; removing said soft resist such that said hard resist is substantially unaffected; and forming a via by etching, using the first opening as a second mask opening, through
said insulating material at bottom of said trench down to said underlying device layer.
Claim 3
Dependent Claim
11 words
The method of claim 1 wherein said hard resist is SiN.
Claim 4
Dependent Claim
31 words
The method of claim 2 further comprising: depositing an anti-reflective layer above said top surface of said hard resist to facilitate
said etching through said soft resist and said insulating material.
Claim 5
Dependent Claim
23 words
The method of claim 3 further comprising: performing a break-through etch of said anti-reflective layer prior to said etching
through said hard resist.
Claim 6
Dependent Claim
19 words
The method of claim 4 wherein said break-through etch employs an etchant
source gas that includes N 2 .
Claim 7
Dependent Claim
27 words
The method of claim 3 wherein said trench has a bottom which extends a predetermined
distance from the top of the upper surface of the insulator layer
Claim 8
Dependent Claim
24 words
The method of claim 6 further comprising etching in accordance with selected
etch parameters through said insulating material at said bottom of said trench.
Claim 9
Dependent Claim
26 words
The method of claim 7 wherein at least one of said selected parameters includes
using an etchant source gas that comprises C 4 F 8 .
Claim 10
Dependent Claim
18 words
The method of claim 7 wherein said selected parameters include a quantity of
O 2 etchant source gas.
Claim 11
Dependent Claim
12 words
The method of claim 1 wherein said substrate represents a silicon wafer.
Claim 12
Dependent Claim
15 words
The method of claim 1 wherein said first opening is achieved by reactive ion
etching.
Claim 13
Dependent Claim
17 words
The method of claim 1 wherein said substrate is employed in the manufacture
of an integrated circuit.
Claim 14
Dependent Claim
19 words
The method of claim 1 wherein said substrate is employed in the manufacture
of a dynamic random access memory.
Claim 15
Independent Claim
133 words
A method of forming a via configured for connecting an underlying device
layer and an overlying conductor of a layer stack said overlying conductor being configured
to be disposed in a trench formed in an insulating layer and spaced apart from said underlying
device layer by insulating material at a bottom of said trench, said method comprising: depositing a hard mask layer composed of silicon oxynitride having a first opening
corresponding to said trench over said top surface of said insulating layer; depositing a soft mask layer on top of said hard mask layer; said soft mask layer having
a second opening corresponding to the location of said via; and forming a via by etching through said insulating material at said bottom of said trench
down to at least said underlying device layer.
Claim 16
Independent Claim
133 words
A method of forming a via configured for connecting an underlying device
layer and an overlying conductor of a layer stack said overlying conductor being configured
to be disposed in a trench formed in an insulating layer and spaced apart from said underlying
device layer by insulating material at a bottom of said trench, said method comprising: depositing a hard mask layer composed of silicon oxynitride having a first opening
corresponding to said trench over said top surface of said insulating layer; depositing a soft mask layer on top of said hard mask layer; said soft mask layer having
a second opening corresponding to the location of said via; and forming a via by etching through said insulating material at said bottom of said trench
down to at least said underlying device layer.
Claim 17
Dependent Claim
30 words
The method of claim 14 wherein said etching through said insulating material
comprises etching in accordance with selected etch parameters through said insulating material
at said bottom of said trench.
Claim 18
Dependent Claim
26 words
The method of claim 15 wherein at least one of said selected parameters
includes using an etchant source gas that comprises C 4 F 8 .
Claim 19
Dependent Claim
21 words
The method of claim 15 wherein at least one of said parameters includes using
an etchant source gas that comprises oxygen.
Claim 20
Dependent Claim
24 words
The method of claim 15 wherein at least one of said parameters includes using
an etchant source gas that comprises argon and carbon monoxide.
Claim 21
Dependent Claim
33 words
The method of claim 14 further comprising depositing conductive material into
said via and said trench to form said overlying conductor and to electrically couple said
overlying conductor with said underlying device layer.
Claim 22
Dependent Claim
17 words
The method of claim 14 wherein said substrate is employed in the manufacture
of an integrated circuit.
Claim 23
Independent Claim
153 words
A method of producing self-aligned vias configured for connecting an
underlying device layer and an overlying conductor of a layer stack, said overlying conductor
being configured to be disposed in a trench formed in an insulating layer and spaced apart
from said underlying device layer by insulating material at a bottom of said trench, said method
comprising: depositing a hard resist having a first opening corresponding to said trench over said
top surface of said insulating layer; depositing a soft resist having a second opening corresponding to the location of said
via and aligned to said first opening; and etching through said insulating layer to form a first trench having a bottom extending
from said top of said insulator layer to a distance about midway of the insulator layer forming a via by etching through said insulating material at said bottom of said first
trench down to at least said underlying device layer.
Claim 24
Independent Claim
153 words
A method of producing self-aligned vias configured for connecting an
underlying device layer and an overlying conductor of a layer stack, said overlying conductor
being configured to be disposed in a trench formed in an insulating layer and spaced apart
from said underlying device layer by insulating material at a bottom of said trench, said method
comprising: depositing a hard resist having a first opening corresponding to said trench over said
top surface of said insulating layer; depositing a soft resist having a second opening corresponding to the location of said
via and aligned to said first opening; and etching through said insulating layer to form a first trench having a bottom extending
from said top of said insulator layer to a distance about midway of the insulator layer forming a via by etching through said insulating material at said bottom of said first
trench down to at least said underlying device layer.
Claim 25
Dependent Claim
17 words
The method of claim 22 wherein said substrate is employed in the manufacture
of an integrated circuit.
Claim 26
Dependent Claim
13 words
The method of claim 22 wherein said device layer represents a conductive
layer.
Claim 27
Dependent Claim
14 words
The method of claim 22 wherein said device layer represents a doped silicon
layer.
References Cited (Backward Citations)
No citation records indexed.
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