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EP0908887A2
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Semiconductor integrated circuit device
Assignee: NEC Electronics Corp
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Filing: 1998-09-11
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Granted: —
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Expires: 2018-09-11
Abstract
Abstract A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.
Inventors
- 👤 Taketo Maesako
- 👤 Kouki Yamamoto
- 👤 Yoshinori Matsui
- 👤 Kenichi Sakakibara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 11:29
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
44 words
A semiconductor memory device comprising a plurality of
memory cell groups each groups being selectable by an address
signal or an internal control signal and a plurality of
registers provided such that data input/output modes for
respective said memory cell groups are set independently.
Claim 2
Dependent Claim
109 words
A semiconductor memory device comprising a main memory
portion composed of a plurality of memory cells arranged in a
plurality of rows and in a plurality of columns, a sub memory
portion composed of a plurality of memory cells arranged in a
plurality of rows and in a plurality of columns, a bi-directional
data transfer circuit for connecting said main
memory portion and said sub memory portion through data
transfer bus lines, respectively, said sub memory portion being
constituted with a plurality of memory cell groups, and a
plurality of registers provided such that different data
input/output modes are set independently for the plurality of
said memory cell groups.
Claim 3
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 1,
wherein the data input/output mode is an address sequence, a
burst length or a latency or a combination of them.
Claim 4
Dependent Claim
31 words
A semiconductor memory device as claimed in claim 1,
wherein said registers for setting the data input/output mode
are provided for a portion or whole portion of said memory cell
groups.
Claim 5
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 1,
wherein an identical data input/output mode can be set in at
least two of said memory cell groups simultaneously.
Claim 6
Dependent Claim
35 words
A semiconductor device comprising memory cells arranged
in a plurality of rows and in a plurality of columns, wherein
the data input/output mode is set simultaneously with an
assignment of a read or write operation.
Claim 7
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 6,
wherein the data input/output mode is an address sequence, a
burst length or a latency or a combination of them.
Claim 8
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 6,
wherein the data input/output mode is set by using an address
other than an address used in the assignment of the read or
write operation.
Claim 9
Dependent Claim
89 words
A semiconductor memory device comprising a main memory
portion constituted with memory cells arranged in a plurality
of rows and in a plurality of columns, a sub memory portion
constructed with memory cells arranged in a plurality of rows
and in a plurality of columns and a bi-directional data
transfer circuit for connecting said main memory portion and
said sub memory portion through data transfer bus lines,
respectively, wherein data input/output modes of said sub
memory portion are set simultaneously with an assignment of a
read or write operation.
Claim 10
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 9,
wherein the data input/output mode is an address sequence, a
burst length or a latency or a combination of them.
Claim 11
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 9,
wherein the data input/output mode is set by using an address
other than an address used in the assignment of the read or
write operation.
References Cited (Backward Citations)
No citation records indexed.
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