Patent EP0897154A2 successfully refreshed from Google Patents.
EP0897154A2
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Memory controller supporting dram circuits with different operating speeds
Assignee: Compaq Computer Corp
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Filing: 1998-08-12
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Granted: —
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Expires: 2018-08-12
Abstract
Abstract A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.
Inventors
- 👤 Sompong P. Olarig
- 👤 Christopher J. Pettey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 16:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1694
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
64 words
A computer system including: a processor, a memory controller coupled to said processor via a host bus; a memory array, including at least two banks of SDRAM memory wherein said
memory controller generates a first clock signal that is provided to a first SDRAM
memory bank and said memory controller generates a second clock signal that is provided
to a second SDRAM memory bank.
Claim 2
Dependent Claim
29 words
The computer system of claim 1, wherein said memory controller includes a first
data queue for buffering data transferred between each of said SDRAM memory banks
and said processor.
Claim 3
Dependent Claim
26 words
The computer system of claim 1 or claim 2, wherein said memory controller
includes a memory clock generator for generating said first and second clock signals.
Claim 4
Dependent Claim
99 words
A computer system including: a processor, a memory controller coupled to said processor by a host bus; a memory array coupled to said memory controller, including at least two banks
of SDRAM memory; said memory controller including a processor control circuit providing a processor
bus clock signal; a memory control circuit providing a memory clock signal; a data queue buffer receiving said system clock signal and said memory clock
signal and transferring data to said processor control synchronized with said processor bus
clock signal, and transferring data to said memory control that is synchronized with said
memory clock signal.
Claim 5
Dependent Claim
30 words
The computer system of claim 4, wherein said memory controller includes a
memory clock generator for generating multiple memory clock signals selective used in
association with said SDRAM memory banks.
Claim 6
Dependent Claim
30 words
The computer system of claim 2, claim 3 or claim 5, wherein said first data queue
buffer temporarily stores data during write cycles from said processor to said SDRAM
memory.
Claim 7
Dependent Claim
26 words
The computer system of claim 6, further including a second data queue for
buffering data signals during read cycles from said SDRAM memory to said processor.
Claim 8
Dependent Claim
22 words
The computer system of claim 1 wherein said first and second clock signals, or said
multiple clock signals operate at different frequencies.
Claim 9
Dependent Claim
34 words
The computer system of claim 7 when dependent on claim 3, wherein said first and
said second data queues include a signal synchronizer for synchronizing signals between
said first and said second clock signals.
Claim 10
Dependent Claim
30 words
The computer system of claim 8, further including a second data queue buffer
which includes a signal synchronizer for synchronizing signals between said processor bus
clock and said memory clock.
Claim 11
Dependent Claim
23 words
The computer system of claim 9 or claim 10, wherein said signal synchronizer
comprises two flip flops that are sequentially or serially connected.
Claim 12
Dependent Claim
19 words
The computer system of claim 11, wherein said flip flops are both clocked by a
processor bus clock signal.
Claim 13
Dependent Claim
18 words
The computer system of claim 11, wherein said flip flops are both clocked by a
memory clock signal.
Claim 14
Dependent Claim
40 words
The computer system of claim 11, wherein said first data queue buffer includes a
plurality of write buffers for storing write data from said processor and said write data is
stored in said write buffers using a system clock signal.
Claim 15
Dependent Claim
24 words
The computer system of claim 14, wherein said write data is written from said
write buffers to said SDRAM using a memory clock signal.
Claim 16
Dependent Claim
46 words
The computer system of claim 15, wherein said first data queue buffer includes
input queue logic and output queue logic, said input queue logic including an input pointer
to said write buffers and said output queue logic including an output queue pointer to said
write buffers.
Claim 17
Dependent Claim
39 words
The computer system of claim 16, wherein said input queue logic includes a buffer
status bit associated with each write buffer, said buffer status bit indicating whether write
data in the associated buffer has been written to SDRAM memory.
Claim 18
Dependent Claim
37 words
The computer system of claim 17, wherein said output queue logic includes a valid
bit associated with each write buffer, said valid bit indicating whether write data in the
associated buffer has been written to SDRAM memory.
Claim 19
Dependent Claim
62 words
The computer system of claim 18, wherein said second data queue includes a
plurality of read buffers for storing the read data and the read data is stored in the read
buffers using said memory clock signal and the read data stored in the read buffers is
extracted from the read buffers and provided to said processor using the system clock
signal.
Claim 20
Dependent Claim
35 words
The computer system of claim 19, wherein said second data queue includes a
pointer to said read buffers, said pointer is incremented upon receipt of an asserted
memory ready signal by said second data queue.
Claim 21
Dependent Claim
58 words
A computer system including: a processor, said processor operation synchronized with a processor bus clock signal; a memory controller coupled to said processor via a host bus; at least one bank of SDRAM memory operating based upon a memory clock signal; and
a memory clock generator that receives a system clock signal and generates the memory
clock signal.
Claim 22
Dependent Claim
49 words
The computer system of claim 21, wherein a plurality of SDRAM memory banks
are provided and said memory clock generator includes a multiplexer coupled to each
bank of SDRAM memory, said multiplexer selecting from a plurality of possible memory
clock signals to provide to each bank of SDRAM memory.
Claim 23
Dependent Claim
23 words
The computer system of claim 22, wherein said memory clock generator includes
a bank speed control register and a memory timing control register.
Claim 24
Dependent Claim
68 words
The computer system of23, wherein serial presence detect information associated
with each bank of SDRAM memory is stored in each SDRAM memory bank and said
memory clock generator includes a data interpreter for receiving said serial presence
detect information from each SDRAM memory bank and said data interpreter stores
values representative of speed in said bank speed control register and timing parameters
in said memory timing control register.
Claim 25
Dependent Claim
41 words
The computer system of claim 24, wherein said multiplexer is controlled by a clock
switch control signal, wherein the state of said clock switch control signal is determined
by said values representative of speed stored in said bank speed control register.
References Cited (Backward Citations)
No citation records indexed.
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