Patent EP0889393A2 successfully refreshed from Google Patents.
EP0889393A2
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Force page zero paging scheme for microcontrollers
Assignee: Microchip Technology Inc
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Filing: 1998-07-03
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Granted: —
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Expires: 2018-07-03
Abstract
Abstract A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on page 0 of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables which are located on page 0 of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in the op-code instruction currently being executed by the microcontroller.
Inventors
- 👤 Randy L. Yach
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 07:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; H; H02; H02J; H02J13/00; H02J13/13; H02J13/1311; H02J13/1313; G06F12/06; G06F12/0615; G06F12/0623; G06F9/3012; G06F9/30138; G06F9/30181; G06F9/30185; G06F9/34; Y; Y02; Y02E; Y02E60/00; Y04; Y04S; Y04S40/00; Y04S40/12; Y04S40/121
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
87 words
A paging scheme for a microcontroller that uses data
random access memory to allow tracking of a currently selected
address in said random access memory comprising the step of
dedicating a bit in each op-code instruction of said
microcontroller which when set forces data access to take place on
a section of said random access memory storing special and general
purpose registers while not affecting current operations of said
microcontroller and not modifying said currently selected address
stored in an op-code instruction being executed by said
microcontroller.
Claim 2
Dependent Claim
43 words
A paging scheme for a microcontroller in accordance
with Claim 1 further comprising the steps of: linearizing an entire address range of said random access
memory; and dedicating a first address section of said random access
memory to special and general purpose registers.
Claim 3
Dependent Claim
45 words
A paging scheme for a microcontroller in accordance
with claim 2 wherein said step of linearizing an entire address
range of said random access memory further comprises the step of
dividing said linearized address range of said random access memory
into a plurality of pages.
Claim 4
Dependent Claim
61 words
A paging scheme for a microcontroller in accordance
with Claim 3 wherein said step of dividing said linearized address
range of said random access memory into a plurality of pages
further comprises the step of dividing said linearized address
range of said random access memory into a plurality of pages
wherein each of said plurality of pages is 256K in size.
Claim 5
Dependent Claim
42 words
A paging scheme for a microcontroller in accordance
with Claim 2 wherein said step of dedicating a bit in each op-code
instruction of said microcontroller further comprises the step of
dedicating a bit in only numeric processing op-code instructions of
said microcontroller.
Claim 6
Dependent Claim
74 words
A paging scheme for a microcontroller in accordance
with Claim 5 wherein said step of dedicating a bit in only numeric
processing op-code instructions of said microcontroller further
comprises the step of removing non-numeric processing op code
instructions from an instruction decode map of said microcontroller
to allow adding said dedicated bit in only said numeric processing
op-code instructions of said microcontroller without increasing a
size of said instruction decode map for said microcontroller.
Claim 7
Dependent Claim
128 words
A paging scheme for a microcontroller that uses data
random access memory to allow tracking of a currently selected
address in said random access memory comprising the steps of: linearizing an entire address range of said random access
memory; dividing said linearized address range of said random
access memory into a plurality of pages; dedicating a first page of said random access memory to
special and general purpose registers; and dedicating a bit in each op-code instruction of said
microcontroller which when set forces data access to take place on
a section of said random access memory storing special and general
purpose registers while not affecting current operations of said
microcontroller and not modifying said currently selected address
stored in an op-code instruction being executed by said
microcontroller.
Claim 8
Dependent Claim
61 words
A paging scheme for a microcontroller in accordance
with Claim 7 wherein said step of dividing said linearized address
range of said random access memory into a plurality of pages
further comprises the step of dividing said linearized address
range of said random access memory into a plurality of pages
wherein each of said plurality of pages is 256K in size.
Claim 9
Dependent Claim
42 words
A paging scheme for a microcontroller in accordance
with Claim 7 wherein said step of dedicating a bit in each op-code
instruction of said microcontroller further comprises the step of
dedicating a bit in only numeric processing op-code instructions of
said microcontroller.
Claim 10
Dependent Claim
71 words
A paging scheme for a microcontroller in accordance
with Claim 9 wherein said stop of dedicating a bit in only numeric
processing op-code instructions of said microcontroller further
comprises the step of removing non-numeric processing op code
instructions from an instruction decode map to allow adding said
dedicated bit in only said numeric processing op-code instructions
of said microcontroller without increasing a size of an instruction
decode map of said microcontroller.
Claim 11
Dependent Claim
106 words
A microcontroller having force page zero
architecture comprising, in combination: random access memory having an entire linearized address
range wherein said random access memory is divided into a plurality
of pages, said random access memory dedicating a first page to
special and general purpose registers; and a dedicated bit in each op-code instruction of said
microcontroller which when set forces data access to take place on
said first page of said random access memory storing said special
and general purpose registers while not affecting current
operations of said microcontroller and not modifying said currently
selected address stored in an op-code instruction being executed by
said microcontroller.
Claim 12
Dependent Claim
28 words
A microcontroller having force page zero
architecture in accordance with Claim 11 wherein each of said
plurality of pages of said random access memory is 256K in size.
Claim 13
Dependent Claim
27 words
A microcontroller having force page zero
architecture in accordance with Claim 11 wherein said dedicated bit
is placed only in numeric processing op-code instructions of said
microcontroller.
References Cited (Backward Citations)
No citation records indexed.
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