Patent EP0886454A2 successfully refreshed from Google Patents.
EP0886454A2
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EP
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Method and apparatus to expand an on-chip fifo into local memory
Assignee: Hewlett Packard Development Co LP
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Filing: 1998-06-10
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Granted: —
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Expires: 2018-06-10
Abstract
Abstract A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.
Inventors
- 👤 Simoni Ben-Michael
- 👤 Yifat Ben-Shahar
- 👤 Michael Ben-Nun
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:03
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L12/5602; G; G06; G06F; G06F5/00; G06F5/06; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L2012/5678; H04L2012/5679; H04L2012/5681
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
116 words
An apparatus for receiving and transmitting data,
comprising: a first memory; a second memory; means, responsive to reception of data, for
writing an entry to a list, said list being maintained
as a queue; means for maintaining a first end and a second
end of said queue in said first memory, said first end
having a next entry to be written thereto, said second
end having a next entry to be read therefrom; and means for maintaining a middle portion of said
queue in said second memory where entries to said
queue are passed from said first memory to said second
memory and back to said first memory as said entries
are passed along said queue.
Claim 2
Dependent Claim
15 words
The apparatus of claim 1 wherein said first memory is
implemented in a semiconductor chip.
Claim 3
Dependent Claim
20 words
The apparatus of claim 2 wherein said first memory is a
plurality of logical banks implemented in said
semiconductor chip.
Claim 4
Dependent Claim
13 words
The apparatus of claim 2 wherein said second memory
comprises a local memory.
Claim 5
Independent Claim
108 words
An apparatus for receiving and transmitting data,
comprising: a semiconductor chip for implementing logic for
storing data; means, responsive to reception of data, for
adding an entry to a list, said list being maintained
as a queue; means for maintaining a first end of said queue
in said semiconductor chip, said first end having a
next entry to be written thereto; means for maintaining a second end of said queue
in said semiconductor chip, said second end having a
next entry to be read, for transmitting data; means for maintaining a portion of said queue in
a local memory, said local memory not implemented in
said semiconductor chip.
Claim 6
Dependent Claim
33 words
The apparatus as in claim 5 further comprising: means for said semiconductor chip to transfer a
plurality of entries in said queue to said local
memory during one access to said local memory.
Claim 7
Dependent Claim
193 words
A node comprising: means for establishing a plurality of virtual
circuits through said node; a semiconductor chip for implementing logic for
operating said plurality of virtual circuits, and for
storing data; means, upon receipt of a packet in a first
virtual circuit of said plurality of virtual circuits,
to receive said packet into a buffer; means, responsive to reception of said packet, to
add an entry to a list of virtual circuits, said list
being maintained for returning a credit to a source
node of said packet, said credit granting permission
to said source node to send another packet in said
first virtual circuit; means for maintaining a first end of said list of
credits in said semiconductor chip, said first end
having a next entry to be written thereto; means for maintaining a second end of said list
of credits in said semiconductor chip, said second end
having a next entry to be read, for sending a next
credit message in a next cell of any virtual circuit;
and means for maintaining a portion of said list of
credits in a local memory, said local memory not
implemented in said semiconductor chip.
Claim 8
Independent Claim
186 words
A method for receiving and transmitting data in a
computerized data store, comprising the steps of: providing one or more first logical data banks on
a semiconductor chip, said first banks to receive data
into a front end of a FIFO queue; providing one or more second logical data banks
on a semiconductor chip, said second banks to transmit
data from a back end of said FIFO queue; providing a memory expansion in a local memory
connected to said semiconductor chip, said memory
expansion to form a middle portion of said FIFO queue; writing data to said first banks; and determining, when said first banks are written to
a predetermined threshold level, to move one of said
first banks to said second banks if at least one of
said second banks is empty and said memory expansion
is empty, to move one of said first banks to said
memory expansion if at least one of said second banks
is empty and said memory expansion is not empty, or to
move one of said first banks to said memory expansion
if said second banks are not empty.
Claim 9
Dependent Claim
62 words
A method of claim 8 further comprising the steps of: reading data from said FIFO queue where data is
read from said right banks if said left banks are
empty, and from said left banks if said left banks are
not empty; and moving data from said expansion if one of said
left banks is empty and said expansion is not empty.
References Cited (Backward Citations)
No citation records indexed.
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