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EP0884599A1
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Programming mode selection with jtag circuits
Assignee: Altera Corp
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Filing: 1998-06-10
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Granted: —
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Expires: 2018-06-10
Abstract
Abstract A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).
Inventors
- 👤 Xiaobao Wang
- 👤 Bonnie Wang
- 👤 Chiakang Sung
- 👤 Khai Nguyen
- 👤 Joseph Huang
- 👤 Richard G. Cliff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318555; H03K19/177; H03K19/17736; H03K19/17744; H03K19/17748; G06; G06F; G06F11/00; G06F11/22; G06F11/2273
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
70 words
A method of configuring a programmable
integrated circuit comprising: providing an instruction to a JTAG instruction
register; passing the instruction to a JTAG boundary scan
control logic block; generating in the JTAG boundary scan control logic
block a control signal; passing the control signal to a programming mode
decoder; and based on the control signal, generating a
programming mode signal to place the programmable integrated
circuit in a configuration mode.
Claim 2
Dependent Claim
15 words
The method of claim 1 wherein the instruction
is not an IEEE 1149.1 STAG instruction
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein the instruction
is shifted serially into the JTAG instruction register.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the instruction
is passed in parallel to the JTAG boundary scan control logic
block.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein the control
signal is not a JTAG scan control signal.
Claim 6
Dependent Claim
23 words
The method of claim 1 further comprising: in the configuration mode, loading configuration
information into the programmable integrated circuit through
non-JTAG external pins.
Claim 7
Dependent Claim
49 words
A programmable integrated circuit comprising: a JTAG state machine; an instruction register coupled to the JTAG state
machine; a JTAG boundary scan control logic block coupled to
the instruction register; and a programming mode decoder coupled to receive a mode
signal from the JTAG boundary scan control logic block,
Claim 8
Dependent Claim
28 words
The programmable integrated circuit of claim 7
wherein the programming mode decoder generates a programming
mode signal based on the mode signal and a mode select pin
input.
Claim 9
Dependent Claim
34 words
The programmable integrated circuit of claim 7
wherein the programmable integrated circuit is placed in a
configuration mode based on an instruction in the instruction
register, and the Instruction is not a JTAG instruction.
Claim 10
Dependent Claim
55 words
The programmable integrated circuit of claim 7
wherein the JTAG boundary scan control logic block comprises: a plurality of NAND gates, one NAND gate to generate
one of a plurality of JTAG scan control signals and the mode
signal, wherein each bit of the instruction is coupled in
parallel to the plurality of NAND gates.
Claim 11
Dependent Claim
28 words
The programmable integrated circuit of claim 10
wherein only one of the plurality of JTAG scan control signals
or the mode signal is asserted based on the instruction.
Claim 12
Dependent Claim
50 words
The programmable integrated circuit of claim 7
wherein the programming mode decoder comprises: a plurality of NAND gates, one NAND gate to generate
one of a plurality of programming mode signals, wherein the
mode select signal and an external mode select input is
coupled to the plurality of NAND gates.
Claim 13
Dependent Claim
27 words
The programmable integrated circuit of claim 12
wherein an enable signal is coupled to the plurality of NAND
gates to enable the plurality of programming mode signals.
Claim 14
Dependent Claim
29 words
The programmable integrated circuit of claim 12
wherein only one of the programming mode signals is asserted
based on the mode select signal and the external mode select
signal.
Claim 15
Dependent Claim
27 words
The programmable integrated circuit of claim 7
wherein every programming mode of the programmable integrated
circuit is selectable by providing an appropriate instruction
to the instruction register.
Claim 16
Dependent Claim
19 words
The use of JTAG circuitry within a programmable
integrated circuit to select a programming mode of the
integrated circuit.
Claim 17
Dependent Claim
26 words
The use of an instruction input to a JTAG
instruction register to place a programmable integrated
circuit into a specific programming mode identified by the
instruction.
Claim 18
Dependent Claim
20 words
The use of JTAG circuits in a programmable
logic device to place the programmable logic device in a
configuration mode.
References Cited (Backward Citations)
EP0639006A1
Cited
EP0828163A1
Cited
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