Patent EP0867820A2 successfully refreshed from Google Patents.
EP0867820A2
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EP
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A design environment and a method for generating an implementable description of a digital system
Assignee: Imec
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Filing: 1998-03-13
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Granted: —
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Expires: 2018-03-13
Abstract
Abstract The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.
Inventors
- 👤 Patrick Schaumont
- 👤 Serge Vernalde
- 👤 Johan Cox
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 16:10
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
87 words
A design apparatus compiled on a computer
environment for generating from a behavioral description of
a system comprising at least one digital system part, an
implementable description for said system, said behavioral
description being represented on said computer environment
as a first set of objects with a first set of relations
therebetween, said implementable description being
represented on said computer environment as a second set of
objects with a second set of relations therebetween, said
first and second set of objects being part of a design
environment.
Claim 2
Dependent Claim
23 words
The design apparatus as recited in claim 1
wherein said first and second set of objects are part of a
single design environment.
Claim 3
Dependent Claim
21 words
The design apparatus as recited in claim 1
or claim 2, wherein said design environment comprises an
Object Oriented Programming Language.
Claim 4
Dependent Claim
16 words
The design apparatus as recited in claim
3, wherein said Object Oriented Programming Language is
C++.
Claim 5
Dependent Claim
27 words
The design apparatus as recited in any of
the claims 1 to 4, wherein said design environment is an
open environment wherein new objects can be created.
Claim 6
Dependent Claim
47 words
The design apparatus as recited in any of
the claims 1 to 5, wherein at least part of the input
signals and output signals of said first set of objects are
at least part of the input signals and output signals of
said second set of objects.
Claim 7
Dependent Claim
43 words
The design apparatus as recited in any of
the claims 1 to 6, wherein at least part of the input
signals and output signals of said behavioral description
are at least part of the input signals and output signals
of said implementable description.
Claim 8
Dependent Claim
31 words
The design apparatus as recited in any of
the claims 1 to 7, wherein said first set of objects has
first semantics and said second set of objects has second
semantics.
Claim 9
Dependent Claim
20 words
The design apparatus as recited in claim
8, wherein said first semantics is a data-vector model
and/or a data-flow model.
Claim 10
Dependent Claim
20 words
The design apparatus as recited in claim
8, wherein said second semantics is a signal flow graph
(SFG) data structure.
Claim 11
Dependent Claim
59 words
The design apparatus as recited in any of
the claims 1 to 10, wherein the impact in said
implementable description of at least a part of the objects
of said second set of objects is essentially the same as
the impact in said behavioral description of at least a
part of the objects of said first set of objects.
Claim 12
Dependent Claim
40 words
The design apparatus as recited in any of
the claims 1 to 11, further comprising means for simulating
the behavior of said system, said means simulating the
behavior of said behavioral description, said implementable
description or any intermediate description therebetween.
Claim 13
Dependent Claim
34 words
The design apparatus as recited in any of
the claims 1 to 12, wherein at least part of said second
set of objects is derived from objects belonging to said
first set of objects.
Claim 14
Dependent Claim
27 words
The design apparatus as recited in any of
the claims 1 to 13, wherein said implementable description
is at least partly obtained by refining said behavioral
description.
Claim 15
Dependent Claim
24 words
The design apparatus as recited in any of
the claims 1 to 14, wherein said implementable description
is an architecture description of said system.
Claim 16
Dependent Claim
31 words
The design apparatus as recited in claim
15, further comprising means for translating said
architecture description into a synthesizable description
of said system, said synthesizable description being
directly implementable in hardware.
Claim 17
Dependent Claim
15 words
The design apparatus as recited in claim
16, wherein said hardware is a semiconductor chip.
Claim 18
Dependent Claim
38 words
The design apparatus as recited in any of
the claims 1 to 17, further comprising means to derive said
first set of objects from a vector description describing
said system as a set of operations on data vectors.
Claim 19
Dependent Claim
16 words
The design apparatus as recited in claim
18, wherein said vector description is a MATLAB
description.
Claim 20
Dependent Claim
22 words
The design apparatus as recited in claim
9, further comprising means for simulating statically or
demand-driven scheduled dataflow on said dataflow
description.
Claim 21
Dependent Claim
40 words
The design apparatus as recited in any of
the claims 1 to 20, further comprising means for clock-cycle
true simulating said digital system using said
dataflow description and/or one or more of said SFG data
structures using an expectation-based simulation.
Claim 22
Dependent Claim
68 words
Method for designing a system comprising
at least one digital part, comprising a refining step
wherein a behavioral description of said system is
transformed into an implementable description of said
system, said behavioral description being represented as a
first set of objects with a first set of relations
therebetween and said implementable description being
represented as a second set of objects with a second set of
relations therebetween.
Claim 23
Dependent Claim
20 words
Method as recited in claim 22, wherein
said refining step comprises translating behavioral
characteristics at least partly into structural
characteristics.
Claim 24
Dependent Claim
31 words
Method as recited in claim 22 or 23,
further comprising a simulation step in which the behavior
of said behavioral description, said implementable
description and/or any intermediate description
therebetween is simulated.
Claim 25
Dependent Claim
35 words
Method as recited in any of the claims 22
to 24, wherein said refining step comprises the addition of
new objects, permitting interaction with existing objects,
and adjustments to said existing objects allowing said
interaction.
Claim 26
Dependent Claim
26 words
Method as recited in any of the claims 22
to 25, wherein said refining is performed in an open
environment and comprises expansion of existing objects.
Claim 27
Dependent Claim
38 words
Method as recited in any of the claims 22
to 26, wherein said refining step comprises a first
refining step wherein said behavioral description is a
data-vector model and is at least partly transformed into a
data-flow model.
Claim 28
Dependent Claim
17 words
Method as recited in claim 27, wherein
said data-flow model is an untimed floating point data-flow
model.
Claim 29
Dependent Claim
31 words
Method as recited in claim 27 or 28,
wherein said refining step further comprises a second
refining step wherein said data-flow model is at least
partly transformed into an SFG model.
Claim 30
Dependent Claim
69 words
Method as recited in any of the claims 22
to 29, wherein said refining step comprises a first
refining step, said first refining step comprising the
steps of determining the input vector lengthsof input, output and
intermediate signals, determining the amount of parallelism of operations that
process input signals to output signals, determination of actors, edges and tokens of said data-flow
model, and determining the wordlength of said tokens.
Claim 31
Dependent Claim
46 words
Method as recited in claim 30, wherein
said step of determining the amount of parallelism
comprises determining the amount of parallelism for every
data vector and reducing the unspecified communication
bandwidth of said data-vector model to a fixed number of
communication buses in said dataflow model.
Claim 32
Dependent Claim
67 words
Method as recited in claim 30, wherein
said step of determination of actors, edges and tokens of
said data- flow model comprises defining one or a group of
data vectors in said first data-vector model as actors;
defining data precedences crossing actor bounds, as edges,
said edges behaving like queues and transporting tokens
between actors; construct a system schedule and run a
simulation on a computer environment.
Claim 33
Dependent Claim
21 words
Method as recited in claim 29, wherein
said second refining step comprises transforming said
tokens from floating point to fixed point.
Claim 34
Dependent Claim
17 words
Method as recited in claim 29, wherein
said SFG model is a timed fixed point SFG model.
Claim 35
Dependent Claim
42 words
Method as recited in any of the claims 22
to 34, wherein said second set of objects with said second
set of relations therebetween are at least partly derived
from said first set of objects with said first set of
relations therebetween.
Claim 36
Dependent Claim
41 words
Method as recited in any of the claims 22
to 35, wherein objects belonging to said second set of
objects are new objects, identical with and/or derived by
inheritance from objects from said first set of objects, or
a combination thereof.
Claim 37
Dependent Claim
28 words
Method as recited in claim 29, further
comprising the step of combining several of said SFG models
with a finite state machine description resulting in an
implementable description.
Claim 38
Dependent Claim
18 words
Method as recited in claim 37, further
comprising the step of transforming said implementable
description to synthesizable code.
Claim 39
Dependent Claim
13 words
Method as recited in claim 38, wherein
said synthesizable code is VHDL code.
Claim 40
Dependent Claim
17 words
Method for simulating a system, wherein a
description of a system is transformed into compilable C++
code.
Claim 41
Dependent Claim
27 words
Method as recited in claim 40, wherein
said description is an SFG data structure and said
compilable C++ code is used to perform clock cycle true
simulations.
Claim 42
Dependent Claim
44 words
Method as recited in claim 40, wherein
said description comprises the combination of several SFG
data structures with a finite state machine description
resulting in an implementable description, said
implement able description being said compilable C++ code
suitable for simulating said system as software.
Claim 43
Dependent Claim
98 words
Method as recited in claim 40, wherein
said simulating comprises a clock-cycle true simulation of
said system being an expectation-based simulation using one
or more SFG data structures, said expectation-based
simulation comprising the steps of: annotating a token age to every token; annotating a queue age to every queue; increasing token age according to the token aging rules
and with the travel delay for every queue that has
transported the token; increasing queue age with the iteration time of the actor
steering the queue, and; checking whether token age is never smaller than queue
age throughout the simulation.
Claim 44
Dependent Claim
24 words
A hardware circuit or a software
simulation of a hardware circuit designed with the design
apparatus of any of the claims 1 to 21.
Claim 45
Dependent Claim
23 words
A hardware circuit or a software
simulation of a hardware circuit designed with the method
of any of the claims 22 to 39.
References Cited (Backward Citations)
No citation records indexed.
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