Patent US4671570A successfully refreshed from Google Patents.
Patent EP0856879A1 successfully refreshed from Google Patents.
EP0856879A1
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Method for fabricating a semiconductor memory capacitor
Assignee: Hitachi Ltd
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Filing: 1998-01-30
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Granted: —
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Expires: 2018-01-30
Abstract
Abstract The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor.This method can be used in conjunction with the formation of a dynamic random access memory array. The capacitor formation begins with a base electrode (18) adjacent an insulating region (26). This base electrode (18) can comprise either polysilicon or a metal. A layer (28) of a first material, such as a siliciding metal, is formed over the base electrode (18) as well as the adjacent insulating region. A self-aligned capacitor electrode (12) can then be formed by reacting the first material (28) with the base electrode (18) and removing unreacted portions of the first material (28) from the insulating region (26). A nitridation process is performed to form a conductive nitride layer (22) that will have a better oxidation resistance than a pure metal or metal silicide electrode. The capacitor is then completed by forming a dielectric layer (16) over the self-aligned capacitor electrode (12) and a second capacitor electrode (14) over the dielectric layer (16).
Inventors
- 👤 Robert Tsu
- 👤 Isamu Asano
- 👤 Shinpei Iijima
- 👤 William R. Mckee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:27
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/696; H10D1/01; H10D1/041; H10D1/042; H10D1/682; H10D1/694; H10P; H10P95/00; H10P95/90; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10D1/711; H10D1/716; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
74 words
A method of forming an integrated circuit capacitor, the
method comprising the steps of: providing a base electrode material adjacent an insulating
region; forming a layer of a first material over the base electrode
material and the adjacent insulating region; forming a self-aligned capacitor electrode by reacting the
first material with the base electrode material; forming a dielectric layer over the self-aligned capacitor
electrode; and forming a second capacitor electrode over the dielectric
layer.
Claim 2
Dependent Claim
12 words
The method of Claim 1 wherein said base electrode material
comprises silicon.
Claim 3
Dependent Claim
13 words
The method of Claim 2 wherein the first material comprises
a siliciding metal.
Claim 4
Dependent Claim
30 words
The method of Claim 3 wherein the siliciding metal is
selected from the group consisting of tantalum, titanium,
aluminum, tungsten, molybdenum, titanium, platinum, palladium,
ruthenium, aluminum, cobalt, and metal alloys.
Claim 5
Dependent Claim
33 words
The method of Claim 3 wherein the step of forming a self-aligned
capacitor electrode includes heating the first material
and the base electrode in an inert gas ambient to form a metal
silicide.
Claim 6
Dependent Claim
15 words
The method of Claim 5 wherein said heating step comprises a
rapid thermal annealing step.
Claim 7
Dependent Claim
21 words
The method of Claim 3 and further comprising the step of
forming a conductive nitride region over the self-aligned
capacitor electrode.
Claim 8
Dependent Claim
20 words
The method of Claim 7 wherein said step of forming a
conductive nitride region comprises a rapid thermal nitridation
step.
Claim 9
Dependent Claim
13 words
The method of Claim 1 wherein the base electrode material
comprises a metal.
Claim 10
Dependent Claim
22 words
The method of Claim 9 wherein the metal is selected from
the group consisting of tungsten, titanium, tantalum, zirconium,
ruthenium and molybdenum.
Claim 11
Dependent Claim
23 words
The method of Claim 9 wherein the step of forming a self-aligned
capacitor electrode comprises the step of nitriding the
metal base electrode.
Claim 12
Dependent Claim
16 words
The method of Claim 11 wherein said step of nitriding
comprises a rapid thermal nitridation step.
Claim 13
Dependent Claim
15 words
The method of Claim 1 wherein said dielectric layer
comprises a high dielectric constant material.
Claim 14
Dependent Claim
12 words
The method of Claim 1 wherein said dielectric layer
comprises tantalum pentoxide.
Claim 15
Dependent Claim
13 words
The method of Claim 1 wherein said dielectric layer
comprises lead zirconium titanate.
Claim 16
Dependent Claim
13 words
The method of Claim 1 wherein said dielectric layer
comprises barium strontium titanate.
Claim 17
Dependent Claim
12 words
The method of Claim 1 wherein said dielectric layer
comprises strontium titanate.
Claim 18
Dependent Claim
38 words
The method of Claim 1 wherein said second capacitor
electrode comprises a material selected from the group
consisting of titanium nitride, titanium aluminum nitride,
tantalum silicide nitride, tantalum silicon nitride, tungsten
silicon nitride, tungsten nitride and molybdenum nitride.
Claim 19
Dependent Claim
37 words
The method of claim 1 wherein the step of forming a self-aligned
capacitor electrode further comprises the step of
removing any unreacted portions of the first material after
reacting the first material with the base electrode material.
Claim 20
Dependent Claim
42 words
An integrated circuit capacitor comprising: a silicon region; a silicide region disposed on the semiconductor region; a conductive nitride region disposed on the silicide
region; a dielectric layer disposed on the silicide layer; and a conductive layer disposed on the dielectric layer.
Claim 21
Dependent Claim
35 words
The capacitor of Claim 20 wherein the silicide layer
comprises a material selected from the group consisting of
tantalum silicide, titanium silicide, aluminum silicide,
tungsten silicide, molybdenum silicide, cobalt silicide, and a
metal alloy silicide.
Claim 22
Dependent Claim
40 words
The capacitor of Claim 20 wherein the conductive nitride
layer comprises a material selected from the group consisting of
tantalum silicon nitride, titanium silicon nitride, tungsten
silicon nitride, molybdenum silicon nitride, cobalt silicon
nitride, titanium aluminum nitride, and tungsten nitride.
Claim 23
Dependent Claim
15 words
The capacitor of Claim 20 wherein the dielectric layer
comprises an oxide and nitride material.
Claim 24
Dependent Claim
27 words
The capacitor of Claim 20 wherein the dielectric layer is
selected from the group consisting of tantalum pentoxide, lead
zirconium titanate, barium strontium titanate, and strontium
titanate.
Claim 25
Dependent Claim
48 words
An integrated circuit capacitor comprising: a semiconductor region; a conductive nitride region disposed on the semiconductor
region, the conductive nitride comprising a material which
includes a refractory metal and silicon; a dielectric layer disposed on the conductive nitride
region; and a conductive layer disposed on the dielectric layer.
Claim 26
Dependent Claim
25 words
The capacitor of Claim 25 wherein the conductive nitride
region comprises a material selected from the group consisting
of tantalum-silicon-nitride, titanium-silicon-nitride, tungsten-silicon-nitride,
molybdenum-silicon-nitride, and cobalt-silicon-nitride.
Claim 27
Dependent Claim
15 words
The capacitor of Claim 25 wherein the dielectric layer
comprises an oxide and nitride layer.
Claim 28
Dependent Claim
27 words
The capacitor of Claim 25 wherein the dielectric layer is
selected from the group consisting of tantalum pentoxide, lead
zirconium titanate, barium strontium titanate, and strontium
titanate.
Claim 29
Independent Claim
92 words
A method of forming a semiconductor structure, said method
comprising the steps of: forming a silicon storage node of a non-planar shape, the
storage node being adjacent an insulating region; forming a siliciding metal layer over the storage node; reacting portions of the metal layer with the storage node
to form a silicide layer; removing unreacted portions of the metal layer from the
insulating region; forming a conductive nitride layer on the silicide layer; forming a dielectric layer on the conductive nitride layer;
and forming a conductive layer over the dielectric layer.
Claim 30
Dependent Claim
18 words
The method of Claim 29 wherein the step of forming a
conductive nitride layer consumes the silicide layer.
Claim 31
Dependent Claim
36 words
The method of Claim 29 wherein the semiconductor region
comprises polysilicon and wherein the dielectric layer comprises
a material selected from the group consisting of tantalum
pentoxide, lead zirconium tantalate, barium strontium titanate,
and strontium titanate.
Claim 32
Dependent Claim
23 words
The method of Claim 29 wherein the step of forming a
conductive nitride comprises reacting the silicide layer within
a nitrogen bearing ambient.
Claim 33
Independent Claim
138 words
A method of forming a memory device, the method comprising
the steps of: providing a silicon substrate; forming a pass transistor at the face of the silicon
substrate, the pass transistor including first and second
source/drain regions and a gate; forming a bit line electrically coupled to the first
source/drain region; forming a storage node base electrode electrically coupled
to the second source/drain region; forming a layer of a first material on the base electrode; reacting the first material with the base electrode to form
a self-aligned storage node; removing any unreacted portions of the first material; reacting the self-aligned storage plate in a nitrogen
bearing ambient so that an outer surface of the storage node
comprises a conductive nitride; forming a dielectric layer over the storage plate; and forming a cell plate conductor over the dielectric layer.
Claim 34
Independent Claim
204 words
A method for manufacturing a capacitor structure of an
integrated semiconductor memory device, said method comprising
the steps of: forming a sacrificial material layer on a semiconductor
substrate; forming a first conductive layer on said sacrificial
material layer; forming a resist layer and an oxide layer on said first
conductive layer; patterning said resist layer and said oxide layer to form a
first pattern; forming a first material layer on said first conductive
layer; etching said first material layer anisotropically to
thereby form a spacer on sidewalls of said first pattern; etching said first conductive layer using said spacer as an
etch-mask and using said sacrificial material layer as an etch
end-point; removing said first pattern; then forming a second conductive layer on the resultant
structure; etching said second conductive layer anisotropically using
said sacrificial material layer as said etch end-point; removing said spacer together with said sacrificial layer
to thereby form a base storage electrode of a capacitor; forming a layer of a first conductive material over the
base storage electrode; producing a self-aligned reaction between the first
conductive material and the base storage electrode; forming a dielectric layer over the first conductive
material; and forming a conductive layer over the dielectric layer.
References Cited (Backward Citations)
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