Patent EP0849801A2 successfully refreshed from Google Patents.
EP0849801A2
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EP
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Semiconductor device having NMOS and PMOS transistors on common substrate and method of fabricating the same
Assignee: NEC Electronics Corp
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Filing: 1997-12-17
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Granted: —
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Expires: 2017-12-17
Abstract
Abstract There is provided a method of fabricating a semiconductor device, comprising the steps, in order, of, forming first well regions (105A, 105B, 105C, 105D) in a semiconductor substrate (101, 201) in all regions in which high-voltage and low-voltage MOS transistors (51, 52, 53, 54) are to be formed, the semiconductor substrate having a first conductivity and the first well regions having a second conductivity, forming an isolation layer (109) for isolating the first well regions from each other, forming high-voltage well regions (110A, 110B) having a first conductivity, and low-voltage well regions (110C, 110D) having first and second conductivity, and forming MOS transistors on the high-voltage and low-voltage well regions. The high-voltage and low-voltage well regions are formed with the isolation layer being used as a mark. The method makes it possible to form low-voltage and high-voltage MOS transistors on a common semiconductor substrate in the smallest number of fabrication steps.
Inventors
- 👤 Toshihiko Ichikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 20:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10D84/859
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
113 words
A semiconductor device comprising: (a) a semiconductor substrate (101, 201) having a first conductivity; (b) a first, low-voltage MOS transistor (52) formed on the semiconductor
substrate; (c) a second, high-voltage MOS transistor (53) formed on the semiconductor
substrate (101, 201) and having a first conductivity; (d) a third, high-voltage MOS transistor (54) formed on the semiconductor
substrate (101, 201) and having a second conductivity, characterized by that both a first electrically conductive region (110A, 210A) containing a channel
region of the third MOS transistor (54) and a second electrically conductive region
(110B, 210B) containing an extended drain region of the second MOS transistor
(53) are electrically independent of the semiconductor substrate (101, 201).
Claim 2
Dependent Claim
26 words
The semiconductor device as set forth in claim 1, wherein the channel
region (110A, 210A) and the extended drain region (110B, 210B) have a common
conductivity.
Claim 3
Dependent Claim
32 words
The semiconductor device as set forth in claim 1, wherein the channel
region (110A, 210A) and the extended drain region (110B, 210B) are both
surrounded by well regions having a second conductivity.
Claim 4
Dependent Claim
63 words
The semiconductor device as set forth in any one of claims 1 to 3, wherein
an insulating film (113B, 113A) formed below gate electrodes (114B, 114A) of the
second and third MOS transistors (53, 54) at least partially has the same
thickness as that of an insulating film (113D, 113C) formed below a gate electrode
(114D, 114C) of the first MOS transistor (52).
Claim 5
Independent Claim
145 words
A method of fabricating a semiconductor device, comprising the steps, in
order, of: (a) forming first well regions (105A, 105B, 105C, 105D) in a semiconductor
substrate (101, 201) in all regions in which high-voltage and low-voltage MOS
transistors (51, 52, 53, 54) are to be formed, the semiconductor substrate (101,
201) having a first conductivity and the first well regions (105A, 105B, 105C,
105D) having a second conductivity; (b) forming an isolation layer (109) on the semiconductor substrate (101, 201)
for isolating the first well regions (105A, 105B, 105C, 105D) from each other; (c) forming high-voltage well regions (110A, 110B) having a first conductivity,
and low-voltage well regions (110C, 110D) one of which has a first conductivity
and another of which has a second conductivity; and (d) forming MOS transistors (51, 52, 53, 54) on the high-voltage and low-voltage
well regions (110A, 110B, 110C, 110D).
Claim 6
Dependent Claim
24 words
The method as set forth in claim 5, wherein the step (b) is first carried out,
and then, the step (a) is carried out.
Claim 7
Dependent Claim
33 words
The method as set forth in claim 5 or 6, wherein the high-voltage and low-voltage
well regions (110A, 110B, 110C, 110D) are formed with the isolation layer
(109) being used as a mark.
Claim 8
Dependent Claim
47 words
The method as set forth in claim 5 or 6, wherein the high-voltage well
regions (110A, 110B) and the low-voltage well region (110C) having a first
conductivity are first formed, and then the low-voltage well region (110D) having
a second conductivity is formed in the step (c).
Claim 9
Dependent Claim
97 words
The method as set forth in claim 5 or 6, wherein the step (d) comprises the
steps of: (d-1) forming insulating films (113) and gate electrodes (114A, 114B, 114C,
114D) for each of the MOS transistors (51, 52, 53, 54); (d-2) forming highly impurity-doped regions having a second conductivity,
the highly impurity-doped regions serving as source (121, 124) and drain (122,
125) electrodes of NMOS transistors (52, 54); and (d-3) forming highly impurity-doped regions having a first conductivity, the
highly impurity-doped regions serving as source (132, 135) and drain electrodes
(133, 136) of PMOS transistors (51, 53).
Claim 10
Dependent Claim
47 words
The method as set forth in claim 5 or 6, wherein the high-voltage and
low-voltage well regions (110A, 110B, 110C, 110D) are formed by ion-implantation
into the semiconductor substrate (101, 201) through an insulating layer (192, 291)
formed on a surface of the semiconductor substrate (101, 201).
Claim 11
Dependent Claim
29 words
The method as set forth in claim 5 or 6, wherein annealing at 1000°C or
greater is all carried out before the high-voltage well regions (110A, 110B) are
formed.
Claim 12
Dependent Claim
69 words
The method as set forth in claim 5 or 6, wherein the high-voltage well
regions (110A, 110B) are concurrently formed, and wherein one (110B) of the
high-voltage well regions serves as an extended drain region of the high-voltage
MOS transistor (53) having a first conductivity, and the other (110A) of the high-voltage
well regions serves as a channel region of the high-voltage MOS transistor
(54) having a second conductivity.
References Cited (Backward Citations)
No citation records indexed.
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