Patent EP0847059A2 successfully refreshed from Google Patents.
EP0847059A2
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EP
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Semiconductor memory
Assignee: Panasonic Holdings Corp
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Filing: 1997-04-11
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Granted: —
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Expires: 2017-04-11
Abstract
Abstract It is an object to present a semiconductor memory device of nonvolatile ferroelectric capable of operating stably without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve this object, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1 V) which may cause loss of data.
Inventors
- 👤 Joji Nakane
- 👤 Nobuyuki Moriwaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:52
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; H; H10; H10B; H10B53/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A semiconductor memory device comprising: a ferroelectric capacitor composed of a ferroelectric, plural memory cells, having single or plural
ferroelectric capacitors provided in each, for storing
information by making use of polarized state of the
ferroelectric, word lines connected to the memory cells, for use in
selection of the memory cells, data lines connected to the memory cells, for use in
reading of the information from the selected memory cell, cell plate lines connected to the memory cells, for
use in reading and rewriting of the information, and voltage stabilizing means for stabilizing the voltage
applied to the cell plate line when rewriting the
ferroelectric capacitor.
Claim 2
Dependent Claim
39 words
A semiconductor memory device of claim 1, wherein
the voltage stabilizing means comprises a diode of which
negative electrode side is connected to the cell plate line,
and positive electrode side is connected to a portion of
grounding potential.
Claim 3
Dependent Claim
38 words
A semiconductor memory device of claim 1, wherein
the voltage stabilizing means comprises an N-type
transistor of which drain is connected to the cell plate
line, and gate and source are connected to a portion of
grounding potential.
Claim 4
Dependent Claim
41 words
A semiconductor memory device of claim 1, wherein
the voltage stabilizing means comprises a second
ferroelectric capacitor of which one electrode side is
connected to the cell plate line, and other electrode side
is connected to a portion of grounding potential.
Claim 5
Dependent Claim
59 words
A semiconductor memory device of claim 1, wherein
the word lines and data lines are arranged in a matrix,
a memory cell array is composed of plural memory cells,
and the cell plate line is disposed parallel to the word
line, and the voltage stabilizing means is the cell plate line
shared at least by the two memory cells.
Claim 6
Dependent Claim
89 words
A semiconductor memory device of claim 1, further
comprising switching means for changing over the electric
connection state between the ferroelectric capacitor and
data lines when selecting the memory cell, wherein the voltage stabilizing means is a transistor
element, and the drain of the transistor element is
connected to one electrode connected to the switching
means out of the electrodes at both ends of the
ferroelectric capacitor, a source is connected to the
plate line, and a gate is connected to a signal line for
precharging the word line.
Claim 7
Dependent Claim
71 words
A semiconductor memory device of claim 1, wherein
the voltage stabilizing means is a resistance element
connected to the data line, and a time constant on the basis
of the resistance value of the resistance element and the
capacity of its data line is set greater than a time
constant on the basis of the parasitic resistance existing
in the cell plate line and the ferroelectric capacitor of
the memory cell.
Claim 8
Dependent Claim
97 words
A semiconductor memory device of claim 1, further
comprising a transistor used as switching element for
setting the potential of the data line at the grounding
potential in rewriting operation, wherein the voltage stabilizing means is a capacity
element connected to the data line, and a time constant on the basis of the capacity of the
capacity element and its data line and the ON resistance
of the transistor is set greater than a time constant on
the basis of the parasitic resistance existing in the cell
plate line and the ferroelectric capacitor of the memory
cell.
References Cited (Backward Citations)
No citation records indexed.
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