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EP0844671B1
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Semiconductor element and semiconductor memory device using the same
Assignee: Hitachi Ltd
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Filing: 1994-08-12
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Granted: 2002-11-27
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Expires: 2014-08-12
Abstract
No abstract record available.
Inventors
- 👤 Kazuo Yano
- 👤 Tomoyuki Ishii
- 👤 Takashi Hashimoto
- 👤 Koichi Seki
- 👤 Masakazu Aoki
- 👤 Takeshi Sakata
- 👤 Yoshinobu Nakagome
- 👤 Kan Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:45
CPC Classifications
H; H10; H10B; H10B12/00; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/06; G11C16/10; G11C16/26; G11C16/28; H10B41/00; H10B41/20; H10B41/40; H10B41/42; H10B41/49; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/40; H10D30/402; H10D30/60; H10D30/68; H10D30/688; H10D30/6891; H10D30/6892; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; G11C2216/00; G11C2216/02; G11C2216/06; G11C2216/08; H10D30/62; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
183 words
A semiconductor element, comprising a source region (19) constituting a source of said semiconductor
element; a drain region (20) constituting a drain of said semiconductor
element; an effective channel region (46) interposed between said
source and said drain region; a gate electrode (51) located over said effective channel
region (46) through a gate insulation film (49, 50) interposed
between said gate electrode (51) and said effective
channel region (46); a carrier confinement region (47) formed in the vicinity
of said effective channel region (46) for confining a carrier;
and a potential barrier (23, 25; 50; 53) surrounding said
confinement region (47), wherein storage of information is
effectuated by holding carrier in said carrier confinement
region (24, 47), characterised by a semiconductor thin film structure
(48) having a thickness not greater than 9 nm and formed of a semiconductor material in
an insulation film (50) between said effective channel region
(46) and said carrier confinement region (47) for preventing
electrons from migrating from said effective channel region
(46) to said carrier confinement region (47) due to a quantum confinement effect in the thickness direction.
Claim 2
Dependent Claim
79 words
A semiconductor memory device, comprising a plurality of
memory cells (MMn) each including a semiconductor element according
to claim 1, wherein said gate electrode of each of
said semiconductor elements is connected to a word wire (W);
a source-drain path of each of said semiconductor elements
being connected between a data wire (D) and an operating potential
point (P); and wherein said plurality of memory cells
(MMn) are controlled via said word wires (W) and said data
wires (D).
Claim 3
Dependent Claim
51 words
A semiconductor memory device, comprising a plurality of
memory cells each including a semiconductor element according
to claim 1; wherein said gate electrode is connected to said
drain; and wherein a source-drain path of each of said semiconductor
elements is connected between a word wire (W) and a
data wire (D).
Claim 4
Dependent Claim
90 words
A semiconductor memory device, comprising a plurality of
memory cells each including a switching element (M25) and a
semiconductor element according to claim 1, wherein a source-drain
path of each of said switching elements (M25) is connected
in series to each of said semiconductor elements between
a data wire (D) and an operating potential point (P);
gate of each of said switching elements (M25) being controlled
via a word wire (W); whereby each of said memory
cells (MM81, MM82)is controlled via said word wire (W) and
said data wire (D).
Claim 5
Dependent Claim
148 words
A semiconductor memory device, comprising a plurality of
memory cells each of which includes a first semiconductor
element (MM41) according to claim 1 and having a source-drain
path connected between a first data wire (D) and an operating
potential point (P); and a second semiconductor element
(MM42) according to claim 1 and having a source-drain path
connected between a second data wire (Dn) and the operating
potential point (P), wherein each of said memory cells stores
as data of logic "1" a state in which a threshold voltage of
said first semiconductor element (MM41) is low while a
threshold voltage of said second semiconductor element (MM42)
is high; and wherein each of said memory cells stores as data
of logic "0" a state in which the threshold voltage of said
first semiconductor element (MM41) is high while the threshold
voltage of said second semiconductor element (MM42) is
low.
Claim 6
Dependent Claim
84 words
A semiconductor memory device according to claim 5,
wherein each of said memory cells further includes first and
second switching elements (M45, M46), said first switching
element (M45) having a source-drain path connected in series
to said first semiconductor element (MM41) between said first
data wire (D) and said operating potential point (P); and
said second switching element (M46) having a source-drain
path connected in series to said second semiconductor element
(MM42) between said second data wire (Dn) and said operating
potential point (P).
Claim 7
Dependent Claim
131 words
A semiconductor memory device, comprising a plurality of
memory cells each including a first semiconductor element
(MM51) according to claim 1 and having a source-drain path
connected between a first data wire (MD51) and an operating
potential point; a plurality of dummy cells each including a
second semiconductor element (MM54) according to claim 1 and
having a source-drain path connected between a second data
wire (MD52) and said operating potential point; and a differential
amplifier (MA51); wherein a signal on said first data
wire (MD51) drives a first input terminal of said differential
amplifier, while a signal on said second data wire
(MD52) drives a second input terminal of said differential
amplifier; and wherein data is read out from said memory cell
by reading an output signal of said differential amplifier.
Claim 8
Dependent Claim
107 words
A semiconductor memory device according to claim 7, a
first amplifier circuit (PA51) connected to said first data
wire (D); a first main data wire (MD51) to which output of
said first amplifier circuit (PA51) is connected; said first
input terminal of said differential amplifier (MA51) being
driven by a signal on said first main data line (MD51); a
second amplifier circuit (PA52) connected to said second data
wire; and a second main data wire (MD52) to which output of
said second amplifier circuit (PA52) is connected; said second input
terminal of said differential amplifier (MA51) being
driven by a signal on said second main data wire.
Claim 9
Dependent Claim
36 words
A semiconductor memory device according to claim 8,
wherein said second amplifier circuit (PA52) is so designed
as to have an output current driving capability which is
smaller than that of said first amplifier circuit (PA51).
References Cited (Backward Citations)
No citation records indexed.
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