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EP0840512A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated audio/video circuitry

Assignee: Texas Instruments Inc
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Filing: 1997-11-03
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Granted: —
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Expires: 2017-11-03
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Abstract

Abstract An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Inventors

  • 👤 Gerard Chauval
  • 👤 Gerard Benbassat
  • 👤 Frank L. Laczko
  • 👤 Y. Paul Chiang
  • 👤 Karen L. Walker

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 23:38
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/80; H04N21/81; H04N21/8166; H04N21/40; H04N21/43; G; G09; G09G; G09G5/00; G09G5/14; G09G5/36; G09G5/39; G09G5/395; H04N19/00; H04N19/42; H04N19/436; H04N19/60; H04N19/61; H04N21/41; H04N21/426; H04N21/42607; H04N21/42615; H04N21/42623; H04N21/42653; H04N21/4302; H04N21/4305; H04N21/431; H04N21/434; H04N21/436; H04N21/4363; H04N21/43632; H04N21/439; H04N21/44; H04N21/443; H04N11/00; H04N11/06; H04N11/20; H04N5/00; H04N5/44

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 141 words
Audio Visual Circuitry, comprising: a transport packet parsing circuit for receiving a transport data packet stream, a processor for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit for moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessor circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

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