An integrated circuit device and method of communication therewith

Claim 2

A single chip integrated circuit device according to claim 1, wherein the data packet converter is further operable to convert parallel data into serial data packets and to allocate a type identifier to said serial packets converted from parallel data from said bus system, in accordance with the information received from said bus system.

Claim 3

A single chip integrated circuit device according to claim 1 or 2 wherein the data packet converter comprises length identification circuitry for determining the length of a serial data packet from the packet identifier.

Claim 4

A single chip integrated circuit device according to any preceding claim wherein the data packet converter comprises message identification circuitry for determining from the packet identifier the type of message conveyed by the serial data packet and for implementing said message by supplying appropriate parallel data to said bus system.

Claim 5

A single chip integrated circuit device according to claim 4 wherein the bus system comprises a plurality of parallel buses and the data packet converter is operable to supply parallel data to a selected one of said parallel buses in dependence on the nature of the message identified by the packet identifier.

Claim 6

A single chip integrated circuit device according to claim 5, wherein the functional circuitry comprises memory interface circuitry for accessing memory local to the chip, and wherein at least one of said buses is a memory bus comprising address lines, data lines and control lines for allowing memory accesses to be implemented to said local memory from the external device.

Claim 7

A single chip integrated circuit device according to claim 5, wherein at least one of said buses in a register access bus for accessing on chip registers.

Claim 8

A single chip integrated circuit device according to claims 6 and 7, wherein when the message is a memory access request, the message includes an address to be accessed and the parallel data is supplied to one of said buses depending on said address.

Claim 9

A single chip integrated circuit device according to claim 7 or 8, wherein the on-chip registers include a control register for interrupting normal operation of the on-chip functional circuitry in dependence on parallel data loaded in the control register from said bus system.

Claim 10

A single chip integrated circuit device according to any preceding claim wherein the functional circuitry comprises a processor.

Claim 11

A single chip integrated circuit device according to any preceding claim wherein the functional circuitry comprises a plurality of processors.

Claim 12

A single chip integrated circuit device according to any preceding claim, in which the external device comprises an external debugging host, and said external port provides an external serial communication link for debugging commands from the external debugging host to the on-chip functional circuitry.

Claim 13

A single chip integrated circuit device according to any preceding claim, in which said external device is provided with a further memory which is local to the external device, and said external port provides a connection operable to allow said on-chip functional circuitry to access said further memory in addition to its local memory.

Claim 14

A single chip integrated circuit device according to claim 10, wherein said external port permits operating code to be supplied from said external device into said local memory for the processor, whereby the processor can be controlled by the external device to execute said operating code.

Claim 15

A single chip integrated circuit device according to any preceding claim which comprises diagnostic control circuitry on-chip connected to said parallel bus system and operable to transmit diagnostic information onto said bus system for supply off-chip via said external port.

Claim 17

A method according to claim 16, wherein parallel data supplied from the on-chip bus system is converted into serial packets for transmission off-chip via a serial output pin of the external port.

Claim 18

A method according to claim 16, wherein a packet identifier is allocated to the serial packets converted from said parallel data in accordance with the information contained in said parallel data.

Claim 20

A method according to claim 19, wherein when the length of a packet is identified as having a bit length wider than the bit width of the bus system, the serial packet is converted into successive sets of parallel data placed sequentially on the bus system.

Claim 21

A single chip integrated circuit device comprising: a bus system for effecting communication of parallel data on chip; functional circuitry connected to said bus system for executing an operation in response to parallel data received from said bus system; an external port comprising a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device, said serial data packets each including a packet identifier denoting the nature of the data packet and information defining an operation to be executed by said functional circuitry; and a serial to parallel data packet converter interconnecting said parallel bus system and said external port and operable to read the packet identifier of serial packets which are input through said port and to convert them into parallel data for supply to said bus system in a manner dependent on the nature of the packet identified by the packet identifier, wherein the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and wherein the parallel data may cause some part of the functional circuitry to execute an operation dependent on said information contained in the serial packets from which it has been converted.