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EP0838858A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

CMOS integrated circuit and method of manufacturing the same

Assignee: Infineon Technologies AG
•
Filing: 1997-08-08
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Granted: —
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Expires: 2017-08-08
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Abstract

Abstract Translated from German Auf einer isolierenden Schicht (2), die auf einer Trägerplatte (1) angeordnet ist, sind Halbleiterinseln (6) angeordnet, die jeweils mindestens eine Si1-xGex-Schicht (4) und eine verspannte Siliziumschicht (5) umfassen, die im wesentlichen die gleiche Gitterkonstante wie die Si1-xGex-Schicht (4) aufweist. Die Halbleiterinseln werden vorzugsweise durch selektive Epitaxie gebildet und umfassen p-Kanal-MOS-Transistoren und/oder n-Kanal-MOS-Transistoren. <IMAGE> Semiconductor islands (6) are arranged on an insulating layer (2), which is arranged on a carrier plate (1), each comprising at least one Si1-xGex layer (4) and a strained silicon layer (5), which essentially comprise has the same lattice constant as the Si1-xGex layer (4). The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and / or n-channel MOS transistors. <IMAGE>

Inventors

  • 👤 Bernhard Dr. Lustig
  • 👤 Herbert Dr. Schäfer
  • 👤 Martin Franosch

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 05:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/01; H10D84/02; H10D86/00; H10D86/201

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