Semiconductor device

Claim 2

A semiconductor device according to claim 1, wherein said semiconductor substrate (15) has a substrate terminal, and said back bias driving means provides said first and second back bias voltages to said substrate terminal.

Claim 3

A semiconductor device according to claim 2, wherein said first channel forming region (16) is fully depleted upon application of a threshold voltage thereto, and said second channel forming region (17) is partially depleted upon application of a threshold voltage thereto.

Claim 4

A semiconductor device according to claim 1, wherein the back bias voltage driving means (30, 31, 32) includes first back bias voltage generating means (30) for generating said first back bias voltage (VBB1), second back bias voltage generating means (31) for generating said second back bias voltage (VBB2), and back bias voltage selecting means (32) coupled to said first and second back bias generating means (30, 31) for selecting one of said first and second back bias voltages (VBB1, VBB2) provided from said first and second back bias generating means (30, 31) in response to a control signal (CNT) indicative of whether said first and second conductivity channel type MOS transistors (11, 12) are in the standby or active state and providing said selected back bias voltage (VBB1, VBB2) to said first and second conductivity channel type MOS transistors (11, 12).

Claim 5

A semiconductor device according to claim 1, wherein said first conductivity channel type MOS transistor is an N channel MOS transistor (11), and said second conductivity channel type MOS transistor is a P channel MOS transistor (12).

Claim 6

A semiconductor device according to claim 5, wherein said N and P channel MOS transistors (11, 12) operate in accordance with power supply and ground voltages (5V, 0V), said first back bias voltage (VBB1) is equal to said ground voltage (0V), and said second back bias voltage (VBB2) is equal to said power supply voltage (5V).

Claim 7

A semiconductor device according to claim 1, wherein said first conductivity channel type MOS transistor is a P channel MOS transistor (12), and said second conductivity channel type MOS transistor is an N channel MOS transistor (11).

Claim 8

A semiconductor device according to claim 7, wherein said P and N channel MOS transistors (12, 11) operate in accordance with power supply and ground voltages (5V, 0V), said first back bias voltage (VBB1) is equal to said power supply voltage (5V), and said second back bias voltage (VBB2) is equal to said ground voltage (0V).

Claim 9

A semiconductor device according to claim 5, wherein the first gate electrode (5) is a first front gate electrode (5); the second gate electrode (5) is a second front gate electrode (5); and the semiconductor device comprises a first back gate electrode (18) opposite to said first front gate electrode (5) and sandwiching said first channel forming region (16) therebetween; a second back gate electrode (19) opposite to said second front gate electrode (5) and sandwiching said second channel forming region (17) therebetween; wherein the back bias driving means (30, 31, 32) is arranged for selectively providing the first back bias voltage (VBB1) and the second back bias voltage (VBB2) to said first back gate electrode (18); and the device further comprises a second back bias driving means (32, 33, 34) arranged for selectively providing a third back bias voltage (VBB2) in the standby state and a fourth back bias voltage (VBB1) such as to enhance a current supplying drivability of said P channel MOS transistor (12) in the active state to said second back gate electrode (19).

Claim 10

A semiconductor device according to claim 9, wherein said first channel forming region (16) is fully depleted upon application of a threshold voltage thereof, and said second channel forming region (17) is fully depleted upon application of a threshold voltage thereof.

Claim 11

A semiconductor device according to claim 9, wherein said first back bias voltage providing means (30-32) includes first back bias voltage generating means (30) for generating said first substrate bias voltage (VBB1), second back bias voltage generating means (31) for generating said second substrate bias voltage (VBB2), and first back bias voltage selecting means (32) coupled to said first and second back bias voltage generating means (30, 31) and said first back gate electrode (18) for selecting one of said first and second back bias voltages (VBB1, VBB2) provided from said first and second back bias voltage generating means (30, 31) in response to a control signal indicative of whether said N and P channel MOS transistors (11, 12) are in the standby or active state and providing said selected back bias voltage to said first back gate electrode (18), and said second back bias voltage providing means (32-34) includes third back bias voltage generating means (33) for generating said third back bias voltage (VBB2), fourth back bias voltage generating means (34) for generating said fourth back bias voltage (VBB1), and second back bias voltage selecting means (32) coupled to said third and fourth back bias generating means (33, 34) and said second back gate electrode (19) for selecting one of said third and fourth back bias voltages (VBB2, VBB1) provided from said third and fourth back bias voltage generating means (33, 34) in response to said control signal (CNT) and providing said selected back bias voltage to said second back gate electrode (19).

Claim 12

A semiconductor device according to claim 9, wherein said N and P channel MOS transistors (11, 12) operate in accordance with power supply and ground voltages (5V, 0V), said first back bias voltage (VBB1) is equal to said ground voltage (0V), said second back bias voltage (VBB2) is equal to said power supply voltage (5V), said third back bias voltage (VBB2) is equal to said power supply voltage (5V), and said fourth back bias voltage (VBB1) is equal to said ground voltage (0V).

Claim 13

A semiconductor device according to claim 9, wherein said first and second back gate electrodes (18, 19) are buried in said insulating layer (14).

Claim 14

A semiconductor device according to any one of claims 1 to 13, wherein said standby state is off state, and said active state is on state.