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EP0827203A2
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EP
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Clock skew minimisation system and method for integrated circuits
Assignee: International Business Machines Corp
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Filing: 1997-07-22
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Granted: —
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Expires: 2017-07-22
Abstract
Abstract A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.
Inventors
- 👤 Ferenc Miklos Bozso
- 👤 Philip George Emma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 12:40
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; H10W; H10W72/00; H10W90/00; H10W90/20; H10W90/28; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/681; H10W70/682; H10W72/01; H10W72/071; H10W72/072; H10W72/07251; H10W72/07252; H10W72/20; H10W72/221; H10W72/227; H10W72/50; H10W72/531; H10W72/536; H10W72/851; H10W72/853; H10W72/859; H10W90/24; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
48 words
A system comprising a primary chip (601) and a secondary chip (603) each having
active components, said primary chip and secondary chip being connected to each
other face-to-face so that I/O pads (604) on at least the secondary chip remain
accessible to connection means outside of the system.
Claim 2
Dependent Claim
18 words
The system in accordance with claim 1, wherein the primary and secondary chips
are coupled via solderballs (600).
Claim 3
Dependent Claim
29 words
The system in accordance with claim 1 or 2, wherein the face of the primary chip
(701) has a smaller area than the face of the secondary chip (702).
Claim 4
Dependent Claim
23 words
The system in accordance with claim 1,2 or 3, wherein the primary and secondary
chips (601,603) are connected face-to-face in an offset manner.
Claim 5
Independent Claim
30 words
The system in accordance with any of Claims 1 to 4 in which said primary chip
contains logic circuitry, and in which said secondary chip contains a clock distribution
network.
Claim 6
Dependent Claim
98 words
The system in accordance with Claim 5, in which said clock distribution network
is a fanout tree with leaf nodes (400) placed on a regular grid, each said leaf node
containing an I/O driver circuit, each said I/O driver circuit driving an I/O pad
centred at said gridpoint corresponding to said leafnode, each said I/O pad being
connected to a corresponding I/O pad on the primary chip, each said I/O pad on said
primary chip serving as a clock input, each said clock input being used to gate storage
elements that are proximate and coupled to that input.
Claim 7
Dependent Claim
33 words
The system in accordance with Claim 6 in which at least one of said I/O driver
circuits further contains a controlling means (903) for delaying the clock input by
fixed amounts of time.
Claim 8
Dependent Claim
37 words
The system in accordance with Claim 7, in which said controlling means stores
state information that specifies one of several fixed amounts of time, said state
information being retained by storage means settable by a scan operation.
Claim 9
Dependent Claim
63 words
The system in accordance with claim 1, wherein at least one of said primary and
secondary chip contains inactive regions and regions of unused wiring tracks on one
or more metal wiring levels in which a plurality of wires in said wiring tracks are
connected to a common ground so that some wires in said wiring tracks are shielded
by said grounded wires.
Claim 10
Independent Claim
51 words
The system of any of claims 1 to 9, further comprising a tertiary chip having a
trench for receiving the primary chip, and wherein the secondary chip is connected to
the tertiary chip face-to-face so that I/O pads on said tertiary chip remain accessible to
connection means outside of the system.
References Cited (Backward Citations)
No citation records indexed.
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