Patent US1179149A successfully refreshed from Google Patents.
Patent EP0822593A2 successfully refreshed from Google Patents.
EP0822593A2
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EP
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A method of manufacturing an insulated gate field effect transistor
Assignee: Siemens AG
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Filing: 1997-07-15
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Granted: —
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Expires: 2017-07-15
Abstract
Abstract A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.
Inventors
- 👤 Manfred Haue
- 👤 Max G. Levy
- 👤 Victor Ray Nastasi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 07:08
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10B12/37; H10P; H10P10/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
83 words
A method for forming Field Effect Transistors (FETs) on a
semiconductor layer of a wafer comprising the steps of: a) forming trenches in a surface of said semiconductor layer; b) forming a dielectric layer on said surface, said dielectric
layer lining said trenches; c) diffusing an oxidation catalyst along said dielectric layer; d) exposing said semiconductor material surface, said dielectric
layer remaining in said trenches; e) forming gate oxide on said exposed semiconductor surface;
and, f) forming FET gates on said gate oxide.
Claim 2
Dependent Claim
66 words
The method of Claim 1 wherein the step (c) of diffusing the
oxidation catalyst comprises the steps of: 1) forming a layer of a conductive material on said dielectric
layer; and 2) chem-mech polishing said conductive material layer with a
slurry containing said oxidation catalyst, said conductive material layer
remaining only in said trenches and said oxidation catalyst diffusing
from said slurry into said dielectric layer.
Claim 3
Dependent Claim
43 words
The method of Claim 2 wherein the step (c) of diffusing the
oxidation catalyst further comprises the step of: 3) reactive ion etching the conductive material such that
conductive material remaining in the trenches is recessed below the
surface of the semiconductor layer.
Claim 4
Dependent Claim
83 words
The method of Claim 3 wherein the step (c) of diffusing the
oxidation catalyst further comprises the steps of: 4) forming an oxide collar in said trenches along said
dielectric layer above said recessed conductive material; 5) forming a second layer of said conductive material on said
recessed conductive material, said second layer filling said recessed
areas of said trenches; and 6) chem-mech polishing said second layer with said slurry until
said conductive material from said second layer remains only in said
trenches.
Claim 5
Dependent Claim
38 words
The method of Claim 4 wherein the step (c) of diffusing the
oxidation catalyst further comprises the step of: 7) reactive ion etching said second conductive material layer
until it is essentially coplanar with said semiconductor layer surface.
Claim 6
Dependent Claim
30 words
The method of Claim 3 wherein the step (c) of diffusing the
oxidation catalyst further comprises the step of: 4) dipping the wafer into a solution containing the oxidation
catalyst.
Claim 7
Dependent Claim
30 words
The method of Claim 5 wherein the step (c) of diffusing the
oxidation catalyst further comprises the step of: 4) dipping the wafer into a solution containing the oxidation
catalyst.
Claim 8
Dependent Claim
19 words
The method of Claim 4 wherein the semiconductor layer is a silicon
layer and the oxidation catalyst is potassium.
Claim 9
Dependent Claim
14 words
The method of Claim 8 wherein the dielectric layer is an Oxide-Nitride-Oxide
(ONO) layer.
Claim 10
Dependent Claim
12 words
The method of Claim 9 wherein said conductive material is doped
polysilicon.
Claim 11
Independent Claim
170 words
A method for forming Field Effect Transistors (FETs) on a silicon
wafer comprising the steps of: a) forming trenches in said silicon wafer; b) forming a dielectric layer on a surface of said silicon
wafer, said dielectric layer lining said trenches; c) forming a polysilicon layer on said dielectric layer; d) chem-mech polishing said polysilicon layer with a slurry
containing an oxidation catalyst, said polysilicon layer remaining only
in said trenches and said oxidation catalyst diffusing from said slurry
into said dielectric layer; e) forming an oxide collar in said trenches along said
dielectric layer above said recessed polysilicon; f) forming a second polysilicon layer along said dielectric
layer on said recessed polysilicon, said second polysilicon layer filling
said trenches; g) chem-mech polishing said second polysilicon layer with said
slurry until said second polysilicon layer remains only in said trenches; h) exposing said silicon surface, said dielectric layer
remaining in said trenches; i) forming gate oxide on said exposed silicon surface; and j) forming FET gates on said gate oxide.
Claim 12
Dependent Claim
35 words
The method of Claim 11 after the step (d) of chem-mech polishing
further comprising the step of: d1) reactive ion etching such that the polysilicon remaining in
the trenches is recessed below the silicon surface.
Claim 13
Dependent Claim
34 words
The method of Claim 12 after the step (g) of chem-mech polishing
further comprising the step of g1) reactive ion etching said second polysilicon layer until it
is essentially coplanar with said silicon surface.
Claim 14
Dependent Claim
28 words
The method of Claim 12 wherein the step (d) of chem-mech polishing
further comprises the step of: d2) dipping the wafer into a solution containing the oxidation
catalyst.
Claim 15
Dependent Claim
28 words
The method of Claim 14 wherein the step (g) of chem-mech polishing
further comprises the step of: g2) dipping the wafer into a solution containing the oxidation
catalyst.
Claim 16
Dependent Claim
11 words
The method of Claim 11 wherein the oxidation catalyst is potassium.
Claim 17
Dependent Claim
14 words
The method of Claim 16 wherein the dielectric layer is an Oxide-Nitride-Oxide
(ONO) layer.
Claim 18
Independent Claim
211 words
A method for forming Field Effect Transistors (FETs) on a silicon
wafer comprising the steps of: a) forming trenches in said silicon wafer; b) forming an Oxide-Nitride-Oxide (ONO) layer on a surface of
said silicon wafer, said ONO layer lining said trenches; c) forming a polysilicon layer on said ONO layer; d) chem-mech polishing said polysilicon layer with a slurry
containing potassium hydroxide, said polysilicon layer remaining only in
said trenches and potassium diffusing from said slurry into said ONO
layer; e) reactive ion etching the polished polysilicon such that
polysilicon remaining in the trenches is recessed below the wafer
surface; f) forming an oxide collar in said trenches along said ONO layer
above said recessed polysilicon; g) forming a second polysilicon layer on said ONO layer and on
said recessed polysilicon, said second layer filling said recessed areas
of said trenches; h) chem-mech polishing said second polysilicon layer with said
slurry until said second polysilicon layer remains only in said trenches; i) reactive ion etching said second polysilicon layer until it
is essentially coplanar with said wafer layer surface; j) exposing said wafer surface, said ONO layer remaining in said
trenches; k) selectively forming gate oxide on said exposed wafer surface;
and l) forming FET gates on said gate oxide.
Claim 19
Dependent Claim
23 words
The method of Claim 18 wherein the step (e) of reactive ion etching
further includes dipping the etched wafer into a KOH solution.
Claim 20
Dependent Claim
23 words
The method of Claim 19 wherein the step (i) of reactive ion etching
further includes dipping the etched wafer into a KOH solution.
References Cited (Backward Citations)
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