Patent EP0820100A2 successfully refreshed from Google Patents.
EP0820100A2
Expired / Lapsed
EP
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Semiconductor device and manufacturing method for the same, basic cell library and manufacturing method for the same, and mask
Assignee: Toshiba Corp
•
Filing: 1997-07-10
•
Granted: —
•
Expires: 2017-07-10
Abstract
Abstract There are provided a semiconductor device, basic cell library, a method for manufacturing a semi-conductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effect correction (OPC), reduce the CAD processing time, perform correction by the OPC for each cell, and reduce the product turn around time. A basic cell registered in the basic cell library has a dummy wiring pattern (4, 41, 42, 43, 44) previously formed on the peripheral portion thereof. With this structure, the distance between a polysilicon gate (3) used in a circuit and the polysilicon wiring of an adjacent dummy wiring pattern in the basic cell can be determined in the cell. As a result, variations in the poly-widths of all of the polysilicon gates in the basic cell due to the optical proximity effect can be estimated, and therefore, a correction value by the OPC on a mask for correcting the gate width based on the variation in the poly-width can be determined in the cell.
Inventors
- 👤 Akira Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 19:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D89/00; H10D89/10; G; G03; G03F; G03F1/00; G03F1/36
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
28 words
A basic cell characterized by comprising an
electrical element; and a dummy wiring pattern (4, 41, 42, 43, 44) formed
on a peripheral portion of said electrical element.
Claim 2
Dependent Claim
28 words
The basic cell according to claim 1, characterized
in that said electrical element has a layout
structure for realizing at least one gate electrode on
a semiconductor substrate.
Claim 3
Dependent Claim
50 words
The basic cell according to claim 1, characterized
in that said dummy wiring pattern (4, 41, 42,
43, 44) has a function of compensating for a variation
in the width of an internal wiring (3) of said basic
cell caused by the dependency of the internal wiring on
the layout.
Claim 4
Dependent Claim
53 words
The basic cell according to claim 1, characterized
in that said basic cell has a layout structure
for compensating for a variation in the width of an
internal wiring (3) thereof due to the optical
proximity effect caused by the internal wiring (3) and
said dummy wiring pattern (4, 41, 42, 43, 44).
Claim 5
Dependent Claim
29 words
The basic cell according to claim 1, characterized
in that said dummy wiring pattern (4, 41, 42)
is placed to surround the whole peripheral portion of
said electrical element.
Claim 6
Dependent Claim
31 words
The basic cell according to claim 1, characterized
in that said dummy wiring pattern (4, 41, 43,
44) is placed in parallel to an internal wiring (3) of
said electrical element.
Claim 7
Dependent Claim
25 words
The basic cell according to claim 1, characterized
in that said dummy wiring pattern (4, 43, 44)
is formed of a plurality of small portions.
Claim 8
Dependent Claim
18 words
The basic cell according to claim 4, characterized
in that the internal wiring (3) is a gate
electrode.
Claim 9
Dependent Claim
35 words
A semiconductor integrated circuit
characterized by comprising at least one basic cell
which includes an electrical element, and a dummy wiring pattern (4, 41, 42, 43, 44) on the
peripheral portion of said electrical element.
Claim 10
Dependent Claim
29 words
The semiconductor integrated circuit according
to claim 9, characterized in that said electrical
element has a layout structure for realizing at least
one gate electrode on a semiconductor substrate.
Claim 11
Dependent Claim
51 words
The semiconductor integrated circuit according
to claim 9, characterized in that said dummy wiring
pattern (4, 41, 42, 43, 44) has a function of compensating
for a variation in the width of an internal
wiring (3) of said basic cell caused by the dependency
of the internal wiring on the layout.
Claim 12
Dependent Claim
53 words
The semiconductor integrated circuit according
to claim 9, characterized in that said basic cell has a
layout structure for compensating for a variation in
the width of an internal wiring (3) due to the optical
proximity effect caused by the internal wiring (3) and
said dummy wiring pattern (4, 41, 42, 43, 44).
Claim 13
Dependent Claim
30 words
The semiconductor integrated circuit according
to claim 9, characterized in that said dummy wiring
pattern (4, 41, 42) is placed to surround the whole
peripheral portion of said basic cell.
Claim 14
Dependent Claim
31 words
The semiconductor integrated circuit according
to claim 9, characterized in that said dummy wiring
pattern (4, 41, 43, 44) is placed in parallel to an
internal wiring of said basic cell.
Claim 15
Dependent Claim
26 words
The semiconductor integrated circuit according
to claim 9, characterized in that said dummy wiring
pattern (4, 43, 44) is formed of a plurality of small
portions.
Claim 16
Dependent Claim
44 words
The semiconductor integrated circuit according
to claim 9, characterized in that said semiconductor
integrated circuit includes a plurality of basic cells
and the dummy cell patterns (4, 41, 42, 43, 44) of said
plurality of basic cells are placed based on the same
rule.
Claim 17
Dependent Claim
35 words
The semiconductor integrated circuit according
to claim 9, characterized in that said dummy wiring
patterns (4, 41, 42, 43, 44) are formed of the same
shape and the same size and in the same arrangement.
Claim 18
Dependent Claim
19 words
The semiconductor integrated circuit according
to claim 12, characterized in that said internal wiring
(3) is a gate electrode.
Claim 19
Dependent Claim
35 words
A basic cell library characterized by comprising
at least one basic cell which includes an
electrical element and a dummy wiring pattern (4, 41, 42, 43, 44) on the
peripheral portion of said electrical element.
Claim 20
Dependent Claim
29 words
The basic cell library according to claim 19,
characterized in that said electrical element has a
layout structure for realizing at least one gate
electrode on a semiconductor substrate.
Claim 21
Dependent Claim
30 words
The basic cell library according to claim 19,
characterized in that said dummy wiring pattern (4, 41,
42) is placed to surround the whole peripheral portion
of said basic cell.
Claim 22
Dependent Claim
32 words
The basic cell library according to claim 19,
characterized in that said dummy wiring pattern (4, 41,
43, 44) is placed in parallel to an internal wiring (3)
of said basic cell.
Claim 23
Dependent Claim
26 words
The basic cell library according to claim 19,
characterized in that said dummy wiring pattern (4, 43,
44) is formed of a plurality of small portions.
Claim 24
Dependent Claim
19 words
The basic cell library according to claim 19,
characterized in that said internal wiring (3) is a
gate electrode.
Claim 25
Independent Claim
59 words
A method for forming a basic cell library
characterized by comprising the steps of preparing a
first basic cell of layout structure for realizing a
plurality of basic gates on a semiconductor substrate;
and forming a second basic cell by placing a dummy
wiring pattern (4, 41, 42, 43, 44) on the peripheral
portion of said first basic cell.
Claim 26
Dependent Claim
40 words
The method for forming a basic cell library
according to claim 25, characterized in that said dummy
wiring pattern (4, 41) has the same width as and
substantially the same length as an internal wiring of
said first basic cell.
Claim 27
Dependent Claim
44 words
The method for forming a basic cell library
according to claim 26, characterized in that portions
of said dummy wiring pattern (4, 41) formed on said
second basic cell and placed in parallel to said
internal wiring are all formed with the same length.
Claim 28
Independent Claim
78 words
A method for manufacturing a semiconductor
integrated circuit (10) characterized by comprising
the steps of preparing first basic cells of layout
structure for realizing a plurality of basic gates on a
semiconductor substrate; forming a second basic cell by placing a dummy
wiring pattern (4, 41, 42, 43, 44) on the region
boundaries of said first basic cells; and laying out a semiconductor integrated circuit on
the semiconductor substrate by use of said first and
second basic cell.
Claim 29
Dependent Claim
60 words
The method for manufacturing a semiconductor
integrated circuit according to claim 28, characterized
in that said second basic cell has a layout structure
for compensating for a variation in the width of an
internal wiring of first basic cells due to the optical
proximity effect caused by the internal wiring and said
dummy wiring pattern (4, 41, 42, 43, 44).
Claim 30
Independent Claim
78 words
A method for manufacturing a semiconductor
integrated circuit comprising the steps of preparing
plural types of basic cells having dummy wiring
patterns (4, 41, 42, 43, 44) formed on the region
boundaries thereof; and selecting at least two basic cells from said
plural types of basic cells, forming a new basic cell
by overlapping parts of the dummy wiring patterns of
the selected basic cells and stocking the newly formed
basic cell in a basic cell layout library.
Claim 31
Dependent Claim
33 words
A mask for manufacturing a semiconductor
integrated circuit characterized by comprising at least
one basic cell portion having a dummy wiring pattern (4,
41, 42, 43, 44) placed on the peripheral portion
thereof.
Claim 32
Dependent Claim
35 words
The mask for manufacturing a semiconductor
integrated circuit according to claim 31, characterized
in that said dummy wiring pattern (4, 41, 42) is placed
to surround the whole peripheral portion of said basic
cell portion.
Claim 33
Dependent Claim
46 words
The mask for manufacturing a semiconductor
integrated circuit according to claim 31, characterized
in that said mask includes a plurality of basic cell
portions and dummy wiring patterns (4, 41, 42, 43, 44)
of the basic cell portions are all placed based on the
same rule.
References Cited (Backward Citations)
No citation records indexed.
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