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EP0811979A2
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EP
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A semiconductor memory device with a large storage capacity memory and a fast speed memory
Assignee: Mitsubishi Electric Corp
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Filing: 1991-09-27
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Granted: —
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Expires: 2011-09-27
Abstract
Abstract A semiconductor memory device containing a cache includes a SRAM (2) as a cache memory, and a DRAM (1) as a main memory. Collective transfer of data blocks is possible between the DRAM array (1) and the SRAM array (2) through a bi-directional transfer gate circuit (3) and through an internal data line (SBL and 16a and 16b). A DRAM row decoder (14) and a DRAM column decoder (15) are provided in the DRAM array (1). A SRAM row decoder (21) and an SRAM column decoder (22) are provided in the SRAM array (2). Addresses of the SRAM array 2 and DRAM array 1 can be independently applied. The data transfer gate includes a latch circuit (1811) for latching data from the SRAM (2) as a high speed memory, an amplifier circuit (1814) and a gate circuit (1815) for amplifying data from the DRAM (1) as a large capacity memory and for transmitting the same to the SRAM, and a gate circuit (1813) responsive to a DRAM write enable signal (AWDE) for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit (1811), write data is transmitted from the gate circuit (1813) to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit (1814) and the gate circuit (1815). This structure realizes a high speed semiconductor memory device which can be applied to a desired mapping method with a small area of occupation.
Inventors
- 👤 Yasuhiro Mitsubishi Denki K.K. Konishi
- 👤 Katsumi Mitsubishi Denki K.K. Dosaka
- 👤 Kouji Mitsubishi Denki K.K. Hayano
- 👤 Masaki Mitsubishi Denki K.K. Kumanoya
- 👤 Akira Mitsubishi Denki K.K. Yamazaki
- 👤 Hisashi Mitsubishi Denki K.K. Iwamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/04; G11C7/00; G11C7/10; G11C7/1006; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G11C11/005; G11C7/1015; G11C7/103; G11C7/1045; G11C2207/00; G11C2207/22; G11C2207/2254
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
220 words
A semiconductor memory device integrated on a semiconductor chip, comprising: a high speed memory array (SMA1 to SMA4) comprising at least one SRAM matrix of rows and columns arranged approximately at the central portion of said chip; a large capacity memory array (MM1 to MM4) comprising at least one DRAM matrix of rows and columns arranged on two opposite sides of said high speed memory array, data transfer means (BTG) arranged between said high speed memory array and said large capacity memory arrays for transferring data between both memory arrays; a data transmitting line (CDB) arranged at the central portion of said chip for transmitting internal data; first column selecting means (SCDA) arranged between said high speed memory array and said large capacity memory for selecting a corresponding column of the high speed memory in accordance with a received first address and for connecting the selected column to said data transmitting line; second column selecting means (DCD) provided between said high speed memory array and said large capacity memory array for selecting a column of said large capacity memory array in accordance with the second address and for connecting thus selected column to said data transferring means; and a data input/output circuit (IOB1 to IOB4) arranged at the central portion of said chip and connected to said data transmitting line.
Claim 2
Dependent Claim
56 words
A semiconductor memory device according to claim 1, wherein said SRAM matrix comprises a plurality of bit line pairs (SBL, SBLT), one for each SRAM column, said bit line pairs each comprising a first portion (SBL) positioned parallel to the SRAM columns and a second portion (SBLT) positioned parallel to the rows of said SRAM matrix.
Claim 3
Dependent Claim
309 words
A semiconductor memory device for inputting and outputting data through an input/output circuit (274) coupled to an internal data line (251; CDB), comprising: a DRAM array (1; 101; MM) including a plurality of dynamic memory cells (DMC) arranged in a matrix of rows and columns; an SRAM array (2; 201; SMA) including a plurality of static memory cells arranged in a matrix of rows and columns; data transferring means (3; BTG; 210) for transferring data between said DRAM array and said SRAM array through a path provided separate from said internal data line; first connecting means (GIO, LIO, DRC, CDD; 102, 103) for simultaneously selecting a plurality of dynamic memory cells from said DRAM array in accordance with a first address, and for coupling thus selected plurality of dynamic memory cells to said transferring means; second connecting means (SBL, SBLT, SRD; 202) for simultaneously selecting a plurality of static memory cells from said SRAM array in accordance with a second address applied independent from said first address, and for coupling thus selected plurality of static memory cells to said transfer means; refresh designating signal generating means (250); refreshing means (291, 292, 293, 253) responsive to said refresh designating signal for refreshing memory cells of said DRAM array by ignoring said first address, said refresh means including means (293) for generating an address for specifying a dynamic memory cell to be refreshed in response to said refresh designating signal; means (264, 274, 202, 203) responsive to an SRAM array access designating signal for accessing a static memory cell selected by said second address of said SRAM array; and means (262 of Fig. 62) responsive to at least one of said refresh designating signal and said SRAM array access designating signal for setting said transferring means to an operation inhibited state to electrically separate said SRAM array from said DRAM array.
Claim 4
Dependent Claim
98 words
A semiconductor memory device including a memory cell array of a plurality of memory cells, comprising setting means (270) for setting data output mode of said semiconductor memory device in accordance with a data output mode designating signal; reading means (DRD, DCD; SRD, SCD) for reading data of a corresponding memory cell of said memory cell array in accordance with an address, and means (272a, 274) activated in response to a data output designating signal for outputting data read by said reading means at different timings in accordance with the data output mode set by said setting means.
Claim 5
Dependent Claim
207 words
A semiconductor memory device having a large capacity memory (100) and a high speed memory (200) integrated on a single chip for inputting and outputting data with an outside of the memory device through an internal data line (251; CDB) comprising: first selecting means (SRD, SCDA; 202, 203) for selecting a plurality of corresponding memory cells of said high speed memory in accordance with a first address; second selecting means (DRD, DCD; 102, 103) for selecting a plurality of corresponding memory cells of the large capacity memory in accordance with a second address applied independent from said first address; transferring means (3; BTG; 210; 80; 90) responsive to a data transfer designating signal for simultaneously transferring data of selected memory cells of said large capacity memory to selected memory cells of said high speed memory through a path which is different from said internal data line; setting means (260) responsive to completion of data transfer by said data transferring means for setting said large capacity memory to a standby state; and means (264) for enabling said first selecting means at a timing earlier than setting by said setting means to the standby state, thereby enabling access to said high speed memory in accordance with another first address.
Claim 6
Dependent Claim
97 words
A semiconductor memory device comprising: a DRAM (100) comprising an array (1; 101; MM1 ∼ MM4) of dynamic memory cells (DMC) arranged in a matrix of rows and columns and divided into a plurality of blocks (MB11 ∼ MB48) of columns; a cache memory (2; 201; SMA1 ∼ SMA4) comprising a plurality of static memory cells arranged in a separate array of rows and columns; and a plurality of internal data transmitting lines (GIO; LGIO, UGIO; GIOa, GIOb) positioned between said blocks of columns in said DRAM for transmitting data between said DRAM and said cache memory.
Claim 7
Dependent Claim
53 words
A semiconductor memory device integrated on a semiconductor chip, comprising: SRAM memory array (2; 201); DRAM memory array (1; 101) and data transfer means (3; BTG; 210) for transferring data between both the memory arrays; and wherein separate external dedicated power pins are respectively provided for said SRAM and said DRAM (Fig. 17).
Claim 8
Dependent Claim
53 words
A semiconductor memory device as recited in claim 7, wherein said SRAM is formed at a central portion of said chip, the dedicated power pins for said SRAM are located at said central portion and the dedicated power pins for said DRAM are located at an end portion of said portion (Fig. 11).
Claim 9
Dependent Claim
70 words
A semiconductor memory device integrated on a semiconductor chip, comprising: a SRAM cache memory array (2; 201; SMA); a DRAM main memory array (1; 101; MM); and a data transfer means (3; BTG; 210) for transferring data between both the memory arrays; wherein said SRAM is formed at a central portion of said chip and external address pins for said SRAM are located corresponding to said central portion (Fig. 17).
Claim 10
Dependent Claim
76 words
A semiconductor memory device integrated on a semiconductor chip, comprising: a SRAM cache memory array (2; 201; SMA); a DRAM main memory array (1; 101; MM) data transfer means (3; BTG; 210) for transferring data between both the memory arrays; input/output means (250, 252, 274, 270) for transferring data between said semiconductor memory device and an external system; and synchronizing means (254, 272) responsive to an externally applied clock signal for synchronizing external data transfer operations.
Claim 11
Dependent Claim
80 words
A semiconductor memory device including a memory cell array of a plurality of memory cells, comprising: input means (322; 322a, 322b) for transferring external data to said memory cell array; output means (320) for transferring data from said memory cell array and setting means (324; 324a, 32ab; 272a, 270) for selecting a configuration of said input means and said output means, said setting means comprising command register means (270) for designating either separate input/output configuration or a common input/output configuration.
Claim 12
Dependent Claim
237 words
A semiconductor memory device integrated on a semiconductor chip comprising: a SRAM cache memory array (2; 201; SMA); a DRAM main memory array (1; 101; MM); data transfer means (3; BTG; 210) for transferring data between both the memory arrays; and control means (260, 262, 264, 272, 291, 292) for setting said semiconductor memory device in a selected operational mode in response to externally applied control signals and to a clock signal applied to said semiconductor memory device independently of an access to said semiconductor memory device, said control means comprising: first means (260, 262, 264) for setting said semiconductor memory device in a standby mode in response to a first combined states of said externally applied control signals at a first timing of said clock signal (Fig. 74); second means (291, 292, 260) for setting said DRAM array in a refreshing operation mode in response to a second combined states (Fig. 74) of said externally applied control signals at the first timing of said clock signal; third means (260, 262, 264, 272) for setting a data transfer operation mode for data transfer between said semiconductor memory device and an external device (CPU) in response to a third combined states of said externally applied control signals at the first timing of said clock signal; and fourth means (260, 262, 264) for setting a data transfer between said SRAM cache memory array and said DRAM main memory array.
Claim 13
Dependent Claim
287 words
A semiconductor memory device as recited in claim 12, wherein said externally applied control signals include a chip enable signal (E#) for indicating that said semiconductor memory device is selected to be accessed, a cache hit signal (CH#) for indicating that said SRAM cache memory array contains data addressed by said external device, a cache inhibit signal (I#) for indicating that an access to said SRAM cache memory array is inhibited, a write enable signal (W#) indicating data writing into said semiconductor memory device and a refresh signal (REF#) for indicating refreshing of said DRAM main memory array, and wherein said first means sets said semiconductor memory device in said standby state when both said chip enable signal and said refresh signal are inactive at a leading edge of said clock signal, said second means sets said DRAM main memory array in said refresh operation mode when said refresh signal is active at said leading edge of said clock signal, said third means sets data transfer mode between said external device and said SRAM cache memory array when said chip enable signal and said cache bit signal both are active at the leading edge of said clock signal and sets data transfer mode between said external device and said DRAM main memory array when said chip enable signal and said cache inhibit signal are both active at the leading edge of said clock signal, and, said fourth means set said data transfer mode between said SRAM cache memory array and said DRAM main memory array when said chip enable signal is active and said cache bit signal , said cache inhibit signal and said refresh signal are all inactive at the leading edge of said clock signal.
Claim 14
Dependent Claim
30 words
A semiconductor memory device as recited in claim 13, wherein said write enable signal designates which is a source of a data transfer in each said data transfer operation mode.
Claim 15
Dependent Claim
228 words
A semiconductor memory device comprising: a DRAM (100) comprising an array (1; 101; MM) of dynamic type memory cells arranged in a matrix of rows and columns and identified by row address and column address, said DRAM array being divided into DRAM blocks (MBi1 ∼ MBi4) of columns, first selecting means (DRD, DCD; 14, 15) for selecting a memory cell in said DRAM array in response to as address for said DRAM, a cache SRAM (200) comprising a SRAM array (2; 201; SMA) of static type memory cells arranged in matrix of rows and columns separate from said DRAM array and identified by row address and column address independently of addresses in said DRAM, said SRAM further comprising bit lines (SBL) corresponding to SRAM columns, second selecting means (21; 22; SCDA, SRD) for selecting a memory cell in said SRAM array in response to an address for said SRAM; and internal data transmitting means (3, LIO, GIO; BTG, LIO, GIO; 210; 16a, 16b, 3) for transferring data between said SRAM array and said DRAM array, said internal data transmitting means including a plurality of data transmitting lines, at least one for each said DRAM block for data transfer between a selected memory cell of a corresponding DRAM block and an SRAM bit line, whereby DRAM memory locations and SRAM memory locations are desirably, associatively mapped with each other.
Claim 16
Dependent Claim
53 words
A semiconductor memory device as recited in claim 15, wherein said internal data transmitting means including a plurality of means (BTG), one for each said SRAM bit line and for each said data transmitting lines, each for interconnecting a selected DRAM column of a corresponding DRAM block to an associated SRAM bit line.
Claim 17
Dependent Claim
65 words
A semiconductor memory device as recited in claim 15, wherein said DRAM blocks comprise first blocks (UAS) and second blocks (LAS) disposed along a direction of said DRAM column, and wherein a data transmitting line (LG10) provided for a second block is arranged to pass through an associated first block in parallel with and adjacent to data transmitting line (UGIO) for the associated first block.
Claim 18
Dependent Claim
204 words
A semiconductor memory device, comprising: a high speed memory (200) including an array (2; 201) of a plurality of static type memory cells (SMC) arranged in a matrix of rows and columns; a large storage capacity memory (100) including a separate array (1; 101) of a plurality of memory blocks (MB) each comprising a plurality of dynamic type memory cells (DMC) arranged in a matrix of rows and columns; data transfer means (3; BTG; 210) for transferring data between said high speed memory and said large storage capacity memory; said large storage capacity memory further including: a plurality of word lines (DWL) each connecting a row of memory cells of said memory blocks, each said word line including a first connecting line (AL) of a relatively low resistivity, a second connecting line (PL) of a relatively high resistivity and a third connecting line (CNT) for connecting said first and said second connecting lines formed at a region (WSR) between adjacent memory blocks, and a plurality of data transmitting lines (GIO; GIOa, GIOb; UGIO, LGIO; 16a, 16b), at least one for each said memory block, formed at said region for connecting a selected memory cell of an associated memory block to said data transfer means.
Claim 19
Dependent Claim
46 words
A semiconductor memory device as recited in claim 18, wherein each said word line is provided in common to memory blocks arranged in a row extending direction, and each said data transmitting line is provided in common to memory blocks arranged in a column extending direction.
Claim 20
Dependent Claim
118 words
A semiconductor memory device comprising: first (MM1 and MM2) and second (MM3, MM4) main memory arrays formed on a semiconductor substrate, a sub memory array (SMA1 to SMA4) formed on said substrate between said first and second main memory arrays a first data transfer means (upper BTG in Fig. 11) formed on said substrate between said first main memory array and said sub memory array for transferring data between said first main memory array and said sub memory array, and a second data transfer means (lower BTG in Fig. 11) formed on said substrate between said second main memory array and said sub memory array for transferring data between said second memory array and said sub memory array.
Claim 21
Dependent Claim
35 words
A semiconductor memory device according to claim 20, wherein said first and second main memory arrays (MM1 to MM4) are DRAM type array, and said sub memory array SMA1 to SMA4) is SRAM type array.
Claim 22
Dependent Claim
63 words
A semiconductor memory device according to claim 20, wherein said first and second main memory arrays comprise a plurality of blocks of columns (MM1 to MM4) respectively, and said sub memory array comprises a plurality of blocks of columns (SMA1, SMA2) corresponding to said first main memory array and a plurality of blocks of columns (SMA3, SMA4) corresponding to said second main memory.
Claim 23
Dependent Claim
139 words
A semiconductor memory device according to claim 20, wherein said sub memory array comprises a first block (SMA1, SMA2) corresponding to said first main memory array (MM1, MM2) and a second block (SMA3, SMA4) corresponding said second main memory array, and further comprises first and second data output lines (upper and lower CDB in Fig. 11), a first transfer gate means (upper SCDA in Fig. 11) formed on said substrate between said first main memory array and said sub memory array for transmitting data read from a selected storage means of said first block to said first data output line, and a second transfer gate means (lower SCDA in Fig. 11) formed on said substrate between said second main memory array and said sub memory array for transmitting data read from a selected storage means of said second block.
Claim 24
Dependent Claim
108 words
A semiconductor memory device according to claim 20, wherein said first and second main memory arrays (MM1 to MM4) are DRAM type arrays, said sub memory array including a first SRAM type array (SMA1, SMA2) corresponding to said first main memory array and a second SRAM type array (SMA3, SMA4) corresponding to said second main memory array, and said semiconductor memory device further comprises a row decoder (SRD1, SRD2) for said SRAM type array formed on said substrate between said first and second SRAM type arrays and for selecting a plurality of storage means arranged in a particular row of said first and second SRAM type array, respectively.
Claim 25
Dependent Claim
113 words
A semiconductor memory device according to claim 24, further comprising a first column decoder (upper SCDA in Fig. 11) for said first SRAM type array formed on said substrate between said first SRAM type array and said first data transfer means (upper BTG in Fig. 11) for selecting a plurality of storage means in a particular column of said first SRAM type array, and a second column decoder (lower SCDA in Fig. 11) for said second SRAM type array formed on said substrate between said second SRAM type array and said second data transfer means and for selecting a plurality of storage means in a particular column of said second SRAM type array.
Claim 26
Dependent Claim
114 words
A semiconductor memory device according to claim 25, further comprising a first column decoder (upper DCD in Fig. 11) for said first main memory array formed on said substrate between said first main memory array (MM1, MM2) and said first data transfer means (upper BTG in Fig. 11) for selecting a plurality of storage means in a particular column of said first main memory array, and a second column decoder (lower DCD in Fig. 11) for said second main memory array formed on said substrate between said second main memory array and said second data transfer means for selecting a plurality of storage means in a particular column of said second main memory array.
References Cited (Backward Citations)
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