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EP0806737A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

In-system programming with two wire interface

Assignee: Lattice Semiconductor Corp
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Filing: 1997-05-06
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Granted: —
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Expires: 2017-05-06
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Abstract

Abstract Program data generated by the host system to be used in programming one or more associated ISPLDs is converted using a first interface from a parallel data format to a serial data string and then transmitted serially to a second interface. In one embodiment, the first and second interfaces employ Universal Asynchronous Receiver/Transmitter (UARTs). The receiving unit converts the serial program data string to a parallel data byte which is then provided to the programming pins of the ISPLD desired to be programmed. Signals indicative of information relating to the operation of one or more of the ISPLDs associated with the host system may be provided to the host system via pin SDO of the asserted ISPLD. In this manner, embodiments in accordance with the present invention may utilize a two-wire transmission scheme, and thus two-wire interfaces, to facilitate programming of the associated ISPLDs. Having the capability to utilize a two-wire transmission scheme, in turn, allows ISPLDs in accordance with the present invention to be programmed using wired transmission schemes such as for instance coaxial, twisted pair, and coaxial as wells as wireless transmission schemes such as for instance radio frequency (RF) and infrared radiation (Ir).

Inventors

  • 👤 Andrew S. Deming
  • 👤 Daniel T. Gardner
  • 👤 James S. Larsen
  • 👤 Bertrand Leigh

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 09:32
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 110 words
A system for programming a programmable logic device, comprising: a host system including a signal source, said signal source providing parallel data at an output port thereof: a first interface having a parallel port connected to said output port of said signal source and having a serial port, said interface converting said parallel data to serial data; transmission means having a first end connected to said serial port of said interface and having a second end; and a second interface having a serial port connected to said second end of said transmission means and having a parallel port coupled to a plurality of programming pins of said programmable logic device.
Claim 2
Dependent Claim 13 words
The system of Claim 1, wherein said transmission means comprises a coaxial line.
Claim 3
Dependent Claim 14 words
The system of Claim 1, wherein said transmission means comprises a twisted pair line.
Claim 4
Dependent Claim 13 words
The system of Claim 1, wherein said transmission means comprises an ethernet line.
Claim 5
Dependent Claim 12 words
The system of Claim 1, wherein said transmission means comprises a modem.
Claim 6
Dependent Claim 33 words
The system of Claim 1, wherein said transmission means comprises: a transmitter connected to said serial port of said first interface; and a receiver connected to said serial port of said second interface.
Claim 7
Dependent Claim 19 words
The system of Claim 6, wherein said transmitter transmits said serial data to said receiver using radio frequency (RF).
Claim 8
Dependent Claim 19 words
The system of Claim 6, wherein said transmitter transmits said serial data to said receiver using infrared radiation (IR).
Claim 9
Dependent Claim 15 words
The system of Claim 1, wherein said first interface comprises an asynchronous receiver/transmitter unit (UART).
Claim 10
Independent Claim 83 words
A method for programming a programmable logic device, said method comprising the steps of: generating program data in a host system, said program data being in parallel form; converting said program data to a first serial string according to a parallel-to-serial conversion protocol; transmitting said first serial string using a transmission means; receiving said first serial string; converting said first serial string to parallel program data according to a serial-to-parallel conversion protocol; and providing said parallel program data to said programmable logic device.
Claim 11
Dependent Claim 14 words
The method of Claim 10, wherein said transmission means comprises a twisted pair line.
Claim 12
Dependent Claim 13 words
The method of Claim 10, wherein said transmission means comprises a coaxial line.
Claim 13
Dependent Claim 13 words
The method of Claim 10, wherein said transmission means comprises an ethernet line.
Claim 14
Dependent Claim 13 words
The method of Claim 10, wherein said transmission means comprises radio frequency (RF).
Claim 15
Dependent Claim 12 words
The method of Claim 10, wherein said transmission means comprises infrared radiation.
Claim 16
Dependent Claim 73 words
The method of Claim 10, further comprising the steps of: generating in said programmable logic device response data; converting said response data into a second serial string according to said parallel-to-serial conversion protocol; transmitting said second serial string according using said transmission means; receiving said second serial string; converting said second serial string to parallel response data according to said serial-to-parallel conversion protocol; and providing said parallel response data to said host system.

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