EP0791965A2
Expired / Lapsed
EP
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Vertical four terminal transistor
Assignee: Vishay Siliconix Inc
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Filing: 1997-02-20
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Granted: —
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Expires: 2017-02-20
Abstract
Abstract A DMOS power transistor has: a source/drain terminal on a bottom surface of a wafer of a first conductivity type; a body region of a second conductivity type, in a top surface of the wafer; drain/source regions of the first conductivity type bounded laterally and from below by the body region; source/drain regions of the first conductivity type bounded laterally by the body region but in electrical contact with the source/drain terminal via a first conductivity type portion of the wafer; and a gate defining openings overlying the drain/source regions and openings overlying the source/drain regions. The gate's size controls channel lengths in the transistor so that channel lengths are insensitive to diffusion caused by thermal processes, and the transistor is easily fabricated on the same chip as other CMOS devices. Contacts for a drain/source terminal, a gate terminal, and a body terminal are formed from a single metal layer overlying the top surface of the wafer. Active regions of the power transistor are laid out in cells. In one embodiment, the drain/source regions are an array of uniformly spaced squares, and the source/drain regions are interspersed between the drain/source regions. The source/drain regions' widths are selected to minimize the resistance per area of the transistor and may be larger than the minimum design rule requirements. <IMAGE>
Inventors
- 👤 Sik K. Lui
- 👤 Kevin Jew
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/837; H10D84/839
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
137 words
A transistor comprising: a semiconductor wafer of a first conductivity type, the semiconductor wafer having a bottom surface and a top surface; a source/drain terminal on the bottom surface of the wafer; a body region of a second conductivity type disposed in the top surface of the wafer; a plurality of drain/source regions of the first conductivity type in the wafer, wherein each drain/source region is bounded laterally and from below by the body region; a plurality of source/drain regions of the first conductivity type in the wafer, wherein each source/drain region is bounded laterally by the body region and is in electrical contact with the source/drain terminal via a first conductivity type portion of the wafer; and a gate overlying the wafer, the gate defining openings overlying the drain/source regions and openings overlying the source/drain regions.
Claim 2
Dependent Claim
49 words
The transistor of claim 1, wherein the wafer comprises: a substrate of the first conductivity type; and an epitaxial layer of the first conductivity type, formed on a top surface of the substrate, wherein the body region, the source/drain regions, and the drain/source regions are in the epitaxial layer.
Claim 3
Dependent Claim
23 words
The transistor of claim 2, wherein the drain/source regions have an effective dopant concentration higher than a dopant concentration of the epitaxial layer.
Claim 4
Dependent Claim
65 words
The transistor of claim 2, further comprising: an insulator which electrically isolates the gate from underlying portions of the epitaxial layer, the insulator defining a first set of openings to portions of the drain/source regions; and a first conducting region which overlies the insulator, makes electrical contact with the drain/source regions through the first set of openings, and is electrically isolated from the body region.
Claim 5
Dependent Claim
51 words
The transistor of claim 4, wherein the insulator defines a second set of openings, and the transistor further comprises a second conducting region overlying the insulator and laterally spaced apart from the first conducting region, the second conducting region making electrical contact with the gate through the second set of openings.
Claim 6
Dependent Claim
54 words
The transistor of claim 5, wherein the insulator defines a third set of openings, and the transistor further comprises a third conducting region overlying the insulator and laterally spaced apart from the first and second conducting regions, the third conducting region making electrical contact with the body region through the third set of openings.
Claim 7
Dependent Claim
24 words
The transistor of claim 5, wherein each of the drain/source regions includes a lightly doped region proximate to a nearest portion of the gate.
Claim 8
Dependent Claim
24 words
The transistor of claim 2, wherein each of the drain/source regions includes a lightly doped region proximate to a nearest portion of the gate.
Claim 9
Dependent Claim
25 words
The transistor of claim 1, wherein the drain/source regions comprise an array of uniformly spaced apart square regions at a top surface of the wafer.
Claim 10
Dependent Claim
42 words
The transistor of claim 9, wherein the source/drain regions comprise rectangular regions interspersed between the drain/source regions at a top surface of the wafer, wherein each source/drain region has two sides about equal in length to a side of the drain/source regions.
Claim 11
Dependent Claim
57 words
The transistor of claim 10, wherein: the drain/source regions are spaced apart by a distance equal to the sum of a first and a second gate width and a width of one of the source/drain regions; and the width of each source/drain region is such that a resistance per area of the transistor is at a minimum.
Claim 12
Dependent Claim
57 words
The transistor of claim 1, wherein: the drain/source regions are spaced apart by a distance equal to the sum of a first and a second gate width and a width of one of the source/drain regions; and the width of each source/drain region is such that a resistance per area of the transistor is at a minimum.
Claim 13
Dependent Claim
148 words
An integrated circuit comprising a power transistor, wherein the power transistor comprises: a semiconductor wafer of a first conductivity type, the semiconductor wafer having a bottom surface and a top surface; a source/drain terminal on the bottom surface of the wafer; a body region of a second conductivity type disposed in the top surface of the wafer; a plurality of drain/source regions of the first conductivity type formed in the wafer, wherein each drain/source region is bounded laterally and from below by the body region; a plurality of source/drain regions of the first conductivity type formed in the wafer, wherein each source/drain region is bounded laterally by the body region and is in electrical contact with the source/drain terminal via a first conductivity type portion of the wafer; and a gate overlying the wafer, the gate defining openings overlying the drain/source regions and openings overlying the source/drain regions.
Claim 14
Dependent Claim
18 words
The integrated circuit of claim 13, further comprising an N channel transistor formed in and on the wafer.
Claim 15
Dependent Claim
18 words
The integrated circuit of claim 14, further comprising a P channel transistor formed in and on the wafer.
Claim 16
Dependent Claim
18 words
The integrated circuit of claim 13, further comprising a P channel transistor formed in and on the wafer.
Claim 17
Dependent Claim
139 words
A process for forming an integrated circuit, comprising the steps of: forming a body region of a second conductivity type in a top surface of a semiconductor wafer of a first conductivity type, the body region encompassing a region of the first conductivity type; forming a gate region overlying the body region, the gate region defining an opening overlying the body region and an opening overlying the region encompassed by the body region; doping the wafer with dopants of the first conductivity type to form a drain/source region and a source/drain region, wherein the gate region acts as a mask that determines the location of the drain/source and source/drain regions, and the source/drain region is located in electrical contact with the region encompassed by the body region; and forming a source/drain terminal on a bottom surface of the wafer.
Claim 18
Dependent Claim
57 words
The process of claim 17, further comprising: forming an insulating layer overlying the gate region; defining an opening in the insulting layer within an area overlying the drain/source region; and forming a conducting layer over the insulating layer, wherein the conducting layer is partly disposed in the opening in the insulating layer and contacts the drain/source region.
Claim 19
Dependent Claim
96 words
The process of claim 18, further comprising: forming in the top surface of the semiconductor wafer a contact region of the second conductivity type, wherein the contact region is in electrical contact with the body region and extends laterally beyond the gate region; defining an opening in the insulting layer within an area overlying the contact region; and patterning the conducting layer to form a first portion in electrical contact with drain/source regions and a second portion in electrical contact with the contact region, wherein the first and second portions are electrically isolated from each other.
References Cited (Backward Citations)
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