Patent EP0790706A2 successfully refreshed from Google Patents.
EP0790706A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory system
Assignee: HP Inc
•
Filing: 1997-01-30
•
Granted: —
•
Expires: 2017-01-30
Abstract
Abstract A field programmable gate array (FPGA) memory system allows the same array of memory (21) to contain both configurable memory and user memory. The FPGA user logic can modify the information contained within the configurable memory and the user memory. The information stored within the configuration memory defines the logic within the user logic. Therefore, the user logic can modify sections of the logic within the user logic. The configuration memory and the user memory share resources such as address decoders, bitlines and sense amplifiers.
Inventors
- 👤 Charles M.C. Tan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 06:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/17704
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
86 words
A FPGA configuration memory system comprising: a user defined logic block comprising a plurality of logic function modules wherein each logic function module comprises a plurality of programmable switch elements; a plurality of sharable memory cells; a plurality of reconfigurable memory cells, each electrically connected to a corresponding programmable switch element so as to configure logic functions within each logic function module, wherein a particular logic function module can modify the reconfigurable memory cells corresponding to the programmable switch elements within the other logic function modules.
Claim 2
Dependent Claim
28 words
A memory system as recited in claim 1, comprising an external controller which can read and write information to the reconfigurable memory cells and the shareable memory cells.
Claim 3
Dependent Claim
142 words
A memory system as recited in claim 2, comprising: a mode line received from the external controller; an address controller for selecting a row of memory cells within a plurality of memory cells comprising the sharable memory cells and the reconfigurable memory cells, the address controller responsive to address inputs from the external controller when the mode line is activated, the address controller responsive to address inputs from the user defined logic block when the mode line is deactivated; and an input/output controller for selecting a column of memory cells within the plurality of memory cells comprising the sharable memory cells and the reconfigurable memory cells, the input/output controller responsive to address inputs from the external controller when the mode line is activated, the input/output controller responsive to address inputs from the user defined logic block when the mode line is deactivated.
Claim 4
Dependent Claim
71 words
A memory system as recited in claim 1, 2 or 3, wherein one of the logic function modules is designated as a master logic function module which can write into the reconfigurable memory cells corresponding to the programmable switch elements within the other logic function modules but no other logic function module can write to the configuration memory cells corresponding to the programmable switch elements within the master logic function module.
Claim 5
Dependent Claim
23 words
A memory system as recited in any preceding claim, wherein the reconfigurable memory cells and the shareable memory cells share memory support circuitry.
Claim 6
Dependent Claim
16 words
A memory system as recited in any preceding claim, wherein the support circuitry comprises sense amplifiers.
Claim 7
Dependent Claim
20 words
A memory system as recited in any one of claims 1 to 5, wherein the support circuitry comprises input/output logic.
Claim 8
Dependent Claim
21 words
A memory system as recited in any one of claims 1 to 5, wherein the support circuitry comprises read/write control logic.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.