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EP0786818A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Thin film transistor of silicon-on-insulator type

Assignee: Panasonic Electric Works Co Ltd
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Filing: 1996-10-16
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Granted: —
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Expires: 2016-10-16
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Abstract

Abstract A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships: 0.4 µm < T1, 0.4 µm ≤ T2 ≤ 1.5 µm, and T2 < T1, The transistor exhibits an improved power dissipation, high breakdown voltage, and a low on-resistance, and also provides advantages in a manufacturing process of the transistor.

Inventors

  • 👤 Yuji Matsushita Electric Works Ltd. Suzuki
  • 👤 Hitomichi Matsushita Electric Works Ltd. Takano
  • 👤 Masahiko Matsushita Electric Works Ltd Suzumura
  • 👤 Yoshiki Matsushita Electric Works Ltd. Hayasaki
  • 👤 Takashi Matsushita Electric Works Ltd. Kishida
  • 👤 Yoshifumi Matsushita Electric Works Ltd. Shirai

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-06 14:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/657; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10D62/117; H10D62/157; H10D64/00; H10D64/111

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 255 words
A thin film transistor of silicon-on-insulator type comprising: a buried oxide layer (20, 20A, 20B) formed on a semiconductor substrate (10, 10A, 10B); a silicon layer (30, 30A, 30B) of a first conductive type formed on said buried oxide layer, said silicon layer having a body region (31, 31A, 31B) of a second conductive type, source region (33, 33A, 33B) of said first conductive type, drain region (32, 32A, 32B) of said first conductive type, and a drift region (34, 34A, 34B) of said first conductive type formed between said source and drain regions, said source region being formed in said body region to be spaced from said buried oxide layer; an upper oxide layer (40, 40A, 40B) formed on said silicon layer; a source electrode (60, 60A, 60B) contacting both of said body region and said source region; a drain electrode (50, 50A, 50B) contacting said drain region; and a gate electrode (70, 70A, 70B) disposed between said source and drain electrodes and spaced from said silicon layer by a thin oxide layer (41, 41A, 41B); wherein said silicon layer is formed with a first portion (38, 38A, 38B) of a thickness (T1) in which said drift region is formed, and a second portion (36, 36A, 36B) of a thickness (T2) in which said body region is formed to reach said buried oxide layer, and wherein said thicknesses (T1) and (T2) are determined so as to satisfy the following relationships: 0.4 µm < T1 0.4 µm ≤ T2 ≤ 1.5 µm T2 < T1.
Claim 2
Dependent Claim 22 words
A thin film transistor as set forth in claim 1, wherein said first and second conductive types are n-type and p-type, respectively.
Claim 3
Dependent Claim 26 words
A thin film transistor as set forth in claim 1, wherein said drift region (34A, 34B) is formed with a lateral linear doping region (35A, 35B).
Claim 4
Dependent Claim 58 words
A thin film transistor as set froth in claim 3, wherein said gate electrode (70A, 70B) has a field plate (71A, 71B) which is short-circuited to said gate electrode, and wherein said gate electrode and field plate extend laterally in a spaced relation from said silicon layer (30A, 30B) and without overlying said linear doping region (35A, 35B).
Claim 5
Dependent Claim 19 words
A thin film transistor as set forth in claim 1, wherein said thickness (T1) is 1 µm or more.
Claim 6
Dependent Claim 90 words
A thin film transistor as set froth in claim 1, wherein said silicon layer (30A, 30B) is formed on its upper surface with a slope (37A, 37B) extending from said second portion (36A, 36B) to said first portion (38A, 38B), said body region (31A, 31B) extending along said slope from said second portion toward said first portion, said gate electrode (70A, 70B) having a field plate (71A, 71B) which extends in parallel with said slope and in a spaced relation from said slope by said thin oxide layer (41A, 41B).
Claim 7
Dependent Claim 37 words
A thin film transistor as set forth in claim 1, wherein said drain region (32, 32A, 32B) is formed in said silicon layer (30, 30A, 30B) to be spaced from said buried oxide layer (20, 20A, 20B).

References Cited (Backward Citations)

US5246870A Cited
US5300448A Cited

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