Patent EP0778556A2 successfully refreshed from Google Patents.
EP0778556A2
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Active matrix electroluminescent display and method of operation
Assignee: Sarnoff Corp
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Filing: 1993-05-28
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Granted: —
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Expires: 2013-05-28
Abstract
Abstract An active matrix electroluminescent display (AMELD) having an improved light emitting efficiency and methods of operating the AMELD to produce gray scale operation are disclosed. The invention is an AMELD comprising a plurality of pixels, each pixel (42) including a first transistor (44) having its gate connected to a select line (46), its source connected to a data line (48) and its drain connected to the gate of a second transistor (50), the second transistor (50) having its source connected to the data line (48) and its drain connected to a first electrode of an electroluminescent (EL) cell. The EL cell's second electrode is connected to alternating high voltage source (59). A method for producing gray scale performance including the step of varying the length of time the second transistor is on while the alternating voltage is applied to the EL cell is also disclosed.
Inventors
- 👤 Roger Green Stewart
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 13:18
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/2007; G09G3/2011; G09G3/22; G09G3/30; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2310/00; G09G2310/02; G09G2310/0243; G09G2310/0259; G09G2310/0264; G09G2310/027; G09G3/2018
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
152 words
In an electroluminescent display comprising an array of pixels, where each pixel contains a circuit for controlling application of energy to an electroluminescent cell associated with each pixel in said array of pixels, a method of providing gray scale illumination during a frame period comprising the steps of: dividing said frame period into a plurality of LOAD periods and a plurality of ILLUMINATE periods, where each LOAD period is followed by an ILLUMINATE period; applying, during each of said LOAD periods, a data signal to said circuit along a data line and applying a select signal to said circuit along a select line; storing, during each of said LOAD periods, said data line signal within said circuit; and applying, during each of said ILLUMINATE periods, a current to said electroluminescent cell and said circuit, where said electroluminescent cell is selectively illuminated in response to said current and said stored data line signal.
Claim 2
Dependent Claim
52 words
The method of claim 1 wherein, during said ILLUMINATE periods, said method further comprises the steps of: applying a gray scale control signal to said data line; and applying said current to said electroluminescent cell when said gray scale control signal has a magnitude that is less than said stored data signal.
Claim 3
Dependent Claim
26 words
The method of claim 2 wherein said gray scale control signal has a linear ramp waveform over the plurality of ILLUMINATION periods within one frame period.
Claim 4
Dependent Claim
36 words
The method of claim 2 wherein said gray scale control signal has a stepped waveform over the plurality of ILLUMINATION periods within one frame period, where each step in the waveform corresponds to one ILLUMINATION period.
Claim 5
Dependent Claim
37 words
The method of claim 1, 2, 3 or 4 wherein said data signal is a digital signal containing a plurality of bits where each bit is applied to said circuit during a plurality of consecutive LOAD periods.
Claim 6
Dependent Claim
44 words
The method of claim 5 wherein a significance of each bit of said data signal corresponds to an amount of energy applied to said electroluminescent cell during each ILLUMINATE period that follows the LOAD period in which each bit is applied to the circuit.
Claim 7
Dependent Claim
201 words
An electroluminescent display comprising an array of pixels, each pixel comprising: a first transistor and a second transistor; said first transistor having a first transistor gate, a first transistor source and a first transistor drain, where said first transistor gate is connected to a select line, said first transistor source is connected to a data line and said first transistor drain is connected to a second transistor gate of said second transistor; said second transistor having said second transistor gate, a second transistor source and a second transistor drain, where said second transistor source is connected to said data line and second transistor drain is connected to an electroluminescent cell; during a LOAD period and when a select line signal on the select line activates the first transistor, said data line supplies, through said first transistor, a data signal to the second transistor gate where said data signal is stored; and during an ILLUMINATE period, said data line supplies a gray scale control signal to said second transistor, when said data signal stored at said second transistor gate exceeds the gray scale control signal on said data line, said second transistor applies energy from a power supply to said electroluminescent cell.
References Cited (Backward Citations)
No citation records indexed.
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