Patent US3379183A successfully refreshed from Google Patents.
Patent EP0777269A2 successfully refreshed from Google Patents.
EP0777269A2
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MOS transistor and fabrication process therefor
Assignee: Sharp Corp
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Filing: 1996-08-15
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Granted: —
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Expires: 2016-08-15
Abstract
Abstract An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.
Inventors
- 👤 Katsuji Iguchi
- 👤 Kenichi Azuma
- 👤 Akio Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 08:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/60; H10D30/0223; H10D30/0225; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/01326; H10D64/018; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/0179; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H10D30/0217
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
175 words
An MOS transistor comprising: a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.
Claim 2
Dependent Claim
41 words
An MOS transistor as set forth in claim 1, wherein the upper insulating film is formed of a material which is able to be etched at a rate 5 to 30 times higher than a material for the lower insulating film.
Claim 3
Dependent Claim
41 words
An MOS transistor as set forth in claim 1, wherein the upper insulating film is formed of a silicon oxide film, and the lower insulating film is formed of a double-layer film comprised of a silicon nitride film/a silicon oxide film.
Claim 4
Dependent Claim
29 words
An MOS transistor as set forth in claim 1, wherein the sidewall insulating layer includes a silicon oxide film and a silicon nitride film covering the silicon oxide film.
Claim 5
Dependent Claim
59 words
An MOS transistor as set forth in claim 1, wherein the upper insulating film is formed of a silicon oxide film, the lower insulating film is formed of a double-layer film comprised of a silicon nitride film/a silicon oxide film, and the sidewall insulating layer includes a silicon oxide film and a silicon nitride film covering the silicon oxide
Claim 6
Dependent Claim
194 words
A process for fabricating an MOS transistor, comprising the steps of: (i) forming a lower insulating film and an upper insulating film on the entire surface of a semiconductor substrate, and forming an opening extending to the lower insulating film in the upper insulating film on a channel region and a periphery portion of the channel region; (ii) forming a sidewall insulating layer of a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating films on a side wall of the opening formed in the upper insulating film, and removing a portion of the lower insulating film which is present in the bottom of the opening and does not underlie the sidewall insulating layer to expose the semiconductor substrate; (iii) forming a gate insulating film on the exposed semiconductor substrate; (iv) forming a gate electrode on the gate insulating film so that at least a portion of the sidewall insulating layer is covered therewith; and (v) removing a portion of the upper insulating film which overlies regions where source/drain regions are to be formed, to form a sidewall spacer contacting a side wall of the gate electrode.
Claim 7
Dependent Claim
49 words
A process as set forth in claim 6, wherein the lower insulating film is formed of a first insulating film and a second insulating film made of a material permitting the second insulating film to be selectively etched with respect to the first insulating film, in the step (i).
Claim 8
Dependent Claim
39 words
A process as set forth in claim 6, wherein the lower insulating film is formed of a silicon nitride film/a silicon oxide film, and the upper insulating film is formed of a silicon oxide film, in the step (i).
Claim 9
Dependent Claim
40 words
A process as set forth in claim 6, wherein the sidewall insulating layer is formed of a silicon nitride film and a silicon oxide film in this order on the upper insulating film including the opening, in the step (ii).
Claim 10
Dependent Claim
120 words
A process as set forth in claim 6, further comprising the step of: (vi) forming source/drain regions by first-ion-implanting at an angle of not less than θ 1 (tan θ 1 = SG/Sh, where SG is a distance between an end of the sidewall spacer and an end of the gate electrode, Sh is the height of the sidewall spacer) and then second-ion-implanting at an angle of not less than θ 2 (tan θ 2 =BS/Sh, where BS is a distance between an end of a bottom surface of the gate electrode facing the channel region and an end of a top surface of the gate electrode) with use of the gate electrode and the sidewall spacer as a mask.
References Cited (Backward Citations)
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