Programmable modem using spread spectrum communication

Claim 2

The system of Claim 1, wherein said at least one memory comprises: • a code phase storage memory, a spreading code storage memory, and a spreading code length storage memory for said transmitter; • a gain control programming memory for said transmitter; • a up-converter frequency memory; • a transmitter modulation procedure selection memory; and • an over-sampling filter interpolation factor memory for said transmitter.

Claim 3

The system of Claim 2, further comprising: • a memory for storage of a code phase, spreading codes and spreading code lengths of said correlator, with a granularity of half a code bit period; • a gain control memory which stores the gain control factor for said receiver; • a down-converter frequency storage memory; • a demodulation procedure selection memory for said receiver; • a decimation factor storage memory for said decimating filter; and • a clock frequency memory for said clock generators.

Claim 4

The system of Claim 3, further comprising means for programming the codes of said correlator block and of said spreader with a maximal code length of 1024.

Claim 5

The system of Claim 4, wherein said up-converter and said down-converter comply with the CORDIC algorithm.

Claim 6

The system as recited in Claim 5, further comprising an external pilot demodulator, an external traffic demodulator, and an external noise estimator.

Claim 7

The system recited in Claim 6, wherein said correlator generates said plurality of output data signals for said external pilot demodulator, said external traffic demodulator and said external noise estimator, said correlator comprising: • a random access memory for storage of a plurality of PN codes comprising a plurality of pilot codes and a plurality of traffic codes; • a pilot correlator coupled to receive an output signal of said decimating filter and which correlates said decimating filter output signal with said pilot codes to generate first output data signals; • a traffic correlator coupled to receive said output signal of said decimating filter and which correlates said decimating filter output signal with said with said traffic codes to generate second output data signals; • a code phase control circuit comprising having an address generation circuit for said random access memory and having a clock inhibit circuit with a cycle of half a code bit period; • a symbol timing circuit having an interrupt signal generator which generates an interrupt signal for said external processor when said plurality of output data signals are ready.

Claim 8

The system as recited in claim 7 further comprising a symbol timing generator, configured as to bypass said symbol timing circuit.

Claim 9

The system of Claim 7, wherein said digital integrated circuit is an application specific integrated circuit.

Claim 10

The system of Claim 9, wherein said application specific integrated circuit is a domain specific integrated circuit.

Claim 11

A method of digitally combining low rate input data signals with accurately defined up-converter and down-converter intermediate frequencies comprising the step of using the system of Claim 4 to program said programmable interpolation factor with a value high enough to obtain accurately defined up-converter and down-converter frequencies.

Claim 13

The method as recited in claim 12, wherein said receiver comprises a receiver chain with a down-converter, a receiver filter, and a gain control; a receiver chain clock generator coupled to said receiver chain; means for programming said receiver chain and said clock generator having a clock frequency storage memory and a code phase storage memory; and a processor programmed to close synchronization of said pilot demodulation, traffic demodulation and noise estimation by calculating the control values for said clock frequency storage memory and said code phase storage memory.

Claim 14

The system of claim 13 further comprising supporting circuitry to form a position determination device.

Claim 15

A method for obtaining spreading code phase acquisition within 1 symbol period with low power consumption using the system as recited in claim 8, comprising the steps of: • loading said spreading codes in said spreading code storage memory; • setting said code length equal to 1; • reading said plurality of output data signals by said symbol timing generator; • performing a spreading code phase acquisition within 1 symbol period, deriving the output of said symbol timing generator; • applying said output to said receiver; • switching the output to said symbol timing circuit; • setting said code length equal to the length of said spreading codes, and disabling said symbol timing generator.

Claim 16

A method for concatenating short spreading codes into spreading codes with a code length higher than the length of said spreading code storage memory, using the system as recited in claim 2 comprising the steps of: • loading the short spreading codes subsequently in said spreading code storage memory, each of the short spreading codes being determined by the offset address in said spreading code storage memory; • concatenating said short spreading codes by addressing said spreading code storage memory in a predefined sequence of offset addresses via said code phase storage memory.

Claim 17

A modem development kit, comprising: • a programmable modem which receives input data signals and modulates and up-converts said input data signals into first intermediate frequency signals and which demodulates and down-converts second intermediate frequency signals into output data signals, said programmable modem comprising an integrated circuit comprising: a transmitter chain which generates first signals at an intermediate frequency, said transmitter chain having a plurality of circuits generating first baseband signals, said transmitter comprising a converter coupled to receive input data and convert said input data into said first serial baseband signals, a spreader, an over-sampling filter, a gain control, and an up-converter with a programmable frequency which converts said baseband signals to said first intermediate frequency signals, a receiver chain which generates a plurality of output data signals, said receiver chain having a down-converter with a programmable frequency which converts said second intermediate frequency signals to second baseband signals, a decimating filter, a gain control, and a correlator to convert said second baseband signals into said plurality of output data signals, and a clock generator coupled to said transmitter chain and to said receiver chain, said clock generator having at least one numerically controlled oscillator; • a programmable digital signal processor; • a field programmable gate array chip; • an analog to digital converter; and • a digital to analog converter; • a radio to up-convert said first intermediate frequency signals to a first radio frequency signal, and to convert a second radio frequency signal to said second intermediate frequency signal; • an external programming device coupled to said programmable modem, to said digital signal processor and to said field programmable gate array, said external programming device providing programming for said digital signal processor, for configuring said field programmable gate array chip, and for said programmable modem; said external programing device further comprising means for initializing said modem development kit; and means for monitoring and means for controlling said modem development kit; and • an interface between said external programming device and said programmable modem.

Claim 18

The modem development kit of Claim 17, wherein said interface comprises a serial interface and/or a parallel interface, and wherein said external programming device is a personal computer, wherein said personal computer maintains a hardware configuration file for said field programmable array and a hardware configuration file for said programmable modem.

Claim 19

The modem development kit of claim 18, wherein said programmable digital signal processor is integrated on said integrated circuit.

Claim 20

The modem development kit of claim 19 further comprising an interface to emulating and debugging programs being implementable on said digital signal processor, said programs being compiled on said external programming device.

Claim 21

A method for customizing a domain specific integrated circuit for an application, using the modem development kit as recited in Claim 17, comprising the steps of: • collecting the specifications of said application; • choosing a first set of programmable parameters; • initializing the field programmable gate array, and the digital signal processor, and the programmable modem with said first set of programmable parameters; • monitoring the behavior of said programmable modem, initialized with said first set of programmable parameters, comprising the steps of introducing a Doppler shift and a crystal offset; • deriving a second set of programmable parameters; • repeating said initialization, said monitoring and said deriving step until a set of parameters is derived which result in functions complying with said specifications.

Claim 22

A method for designing an application specific integrated circuit, using the modem development kit as recited in Claim 17, comprising the steps of: • collecting the specifications of said application; • choosing a first set of programmable parameters; • initializing the field programmable gate array, the digital signal processor, and the programmable modem with said first set of programmable parameters; • monitoring the behavior of said domain specific integrated circuit, initialized with said first set of programmable parameters, comprising the steps of introducing a Doppler shift and a crystal offset; • deriving a second set of programmable parameters; • repeating said initialization, said monitoring and said deriving steps until a set of parameters is derived which result in functioning for said domain specific integrated circuit according to said specifications; and • designing the application specific integrated circuit according to the set of programmable parameters.

Claim 23

The method as recited in Claim 21, wherein the steps of specifiying said application specific integrated circuit comprises: • selecting a modulation scheme; • switching the filters on or off; • determining the over-sampling factor; • determining the decimation factor; • determining the transmitter intermediate frequency; • determining the bandwidth of the PN code bit frequency PLL; • determining the bandwidth of the carrier frequency PLL; • determining the gain of the PN code bit frequency PLL; • determining the gain of the carrier frequency PLL; determining the PN code length; • determining the tracking update rate; • determining the symbol rate; • determining the PN code set.