A memory sensing circuit employing multi-current mirrors

Claim 2

A circuit as in claim 1, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 3

A circuit as in claim 2, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 4

A circuit as in claim 1, wherein said second current source in each branch is a programmable reference current source.

Claim 5

A circuit as in claim 1, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 6

A circuit as in claim 4, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 7

A circuit as in claim 4, wherein said programmable reference current source is provided by a conduction current of a memory cell, said conduction current having conduction current designating a memory state thereof.

Claim 8

A circuit as in claim 7, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 9

A circuit as in claim 4, wherein said programmable reference current source is duplicated from an original programmable reference current source by a circuit which comprises: first and second one-to-one current mirror means each having only one branch for each of its two legs, said first and second one-to-one current means being interconnected by one of their two legs, and said second current source being provided by connection to the other leg of the second one-to-one current mirror means; and an original programmable reference current source for providing a reference current, said original programmable reference current source being connected to the other leg of the first one-to-one current mirror means, thereby mirroring substantially similar reference current into the interconnected leg, and in turn mirroring same into the other leg of the second one-to-one current means, thereby providing said second current source with substantially similar current as that of the original programmable reference current source.

Claim 10

A circuit as in claim 9, wherein said test current is provided by a conduction current of a memory cell designating a memory state thereof.

Claim 11

A circuit as in claim 10, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 12

A circuit as in claim 9, wherein said programmable reference current source is provided by a memory cell having conduction current designating a memory state thereof.

Claim 13

A circuit as in claim 12, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 14

A circuit as in claim 9, wherein the one-to-many current mirror means and the first one-to-one current mirror means comprise transistors having the same polarity, and the second one-to-one current mirror means comprise transistors having the opposite polarity.

Claim 15

A circuit as in claim 1, wherein said second current source for providing a predetermined reference current in each branch comprises: a transistor of a predetermined size having a source, a drain and a gate; and means for applying a predetermined reference voltage to the gate for producing one of the predetermined reference currents through the source and drain of the transistor of predetermined size; said predetermined reference voltage being constant across the branches and said predetermined size differing across the branches so as to produce the plurality of predetermined reference currents among the branches.

Claim 16

A circuit as in claim 15, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 17

A circuit as in claim 16, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 18

A circuit as in claim 15, wherein said constant reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 19

A circuit as in claim 18, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 20

A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a lowest reference current level thereof, comprising: a one-to-many current mirror means for reproducing a test current into one or more reproduced currents, said current mirror having a first leg for carrying the test current and a second leg comprising a plurality of branches, such that each branch is associated with a reference current level and a multiplication factor; a first current source at each branch for reproducing a reproduced current therein, said reproduced current being scalable from the test current in the first leg by the associated multiplication factor; a second current source at each branch for providing a highest reference current level from among said plurality of reference current levels; and means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current scaled from the test current provided by the first current source has magnitude greater or less than that of the highest reference current provided by the second current source.

Claim 21

A circuit as in claim 20, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 22

A circuit as in claim 21, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 23

A circuit as in claim 20, wherein said highest reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 24

A circuit as in claim 23, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 25

A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a given reference current level thereof, comprising: a one-to-many current mirror means for reproducing the given reference current level into one or more reproduced currents, said current mirror having a first leg for carrying the given reference current and a second leg comprising a plurality of branches, such that each branch is associated with a reference current level and a multiplication factor; a first current source at each branch for reproducing a reproduced current therein, said reproduced current being scalable from the given reference current level in the first leg by the associated multiplication factor; a second current source at each branch for providing the test current; and means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current scaled from the lowest reference current level provided by the first current source has magnitude greater or less than that of the test current provided by the second current source.

Claim 26

A circuit as in claim 25, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 27

A circuit as in claim 26, wherein said memory cell is an EEprom or a Flash EEprom.

Claim 28

A circuit as in claim 25, wherein said lowest reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

Claim 29

A circuit as in claim 28, wherein said memory cell is an EEprom or a Flash EEprom.