Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
341 words
Process for forming an integrated circuit in a
monocrystalline silicon substrate(4) of the type in which
is provided for the formation of at least one matrix of
non-volatile memory cells (1) in each of which a floating
gate and a control gate, both electroconductive, are
insulated electrically from each other by means of an
intermediate dielectric multilayer comprising a lower
silicon oxide layer (7), an intermediate silicon nitride
layer (8) and an upper silicon oxide layer (10) and the
simultaneous implementation in peripheral zones of the
memory cells of at least a first (2) and a second (3)
transistors type having gate dielectric of a first and a
second thickness respectively, wherein after formation of the floating gate
with a gate oxide layer (5) and a polycrystalline silicon
layer (6) and the formation of the lower silicon oxide
layer (7) and the intermediate silicon nitride layer (8),
it comprises the step of: removal of the gate oxide layer (5), the
polycrystalline silicon layer (6), the lower silicon oxide
layer (7) and the intermediate silicon nitride layer (8)
from the zones (R2,R3) peripheral to the matrix; formation of a first silicon oxide layer (9) on the
substrate in the areas (R2,R3) of both transistor types
(2,3); removal of the first silicon oxide layer (9) from
areas (R3) assigned only to the transistors (3) of the
second type; deposition of said upper silicon oxide layer (10) on
the memory cells (1), on the first silicon oxide layer (9)
in the areas (R2) of the transistors (2) of the first type
and on the substrate (4) in the areas (R3) of the
transistors of the second type; and subsequent formation of a second silicon oxide layer
(11) in the areas (R2,R3) of both types of peripheral
transistors (2,3) which allows the growth of a thermal
silicon oxide in the areas of the peripheral transistors
(2,3) between the deposited upper silicon oxide layer (10)
and the substrate (4), said formation of the second silicon
oxide layer (11) comprising a high-temperature treatment in
an oxidizing ambient.
Claim 2
Dependent Claim
43 words
Process in accordance with claim 1 and characterized
in that said high-temperature treatment is performed in an
oxidizing ambient at a temperature between 750°C and 950°C
in an atmosphere containing at least one of the following
compounds O 2 and H 2 O.
Claim 3
Dependent Claim
24 words
Process in accordance with claim 1 and characterized
in that formation of said first silicon oxide layer (9)
comprises a step of high-temperature oxidation.
Claim 4
Dependent Claim
43 words
Process in accordance with claim 3 and characterized
in that said oxidation operation is performed in an
oxidizing ambient at a temperature between 750°C and 950°C
in an atmosphere containing at least one of the following
compounds O 2 and H 2 O.
Claim 5
Dependent Claim
23 words
Process in accordance with claim 1 and characterized
in that it comprises a step of high-temperature nitridizing
of the second silicon oxide layer.
Claim 6
Dependent Claim
85 words
Process in accordance with claim 1 and characterized
in that removal of the first silicon oxide layer (9) from
areas (R3) of the transistors (3) of the second type
comprises a first step of partial removal of said layer (9)
in said areas (R3) and a successive removal step on
portions of the silicon chip at least including regions
(R1,R2) not subjected to the first removal step up to
completion in the above mentioned areas (R3) of removal of
the first silicon oxide layer (9).
Claim 7
Dependent Claim
16 words
Process in accordance with claim 1 and characterized
in that it is implemented with CMOS technology.
Claim 8
Dependent Claim
43 words
Process in accordance with claim 1 and characterized
in that the thickness of said upper deposited silicon oxide
layer (10) is between 5nm and 25nm and that said first and
said second thicknesses of the gate dielectric (9-11;10-11)
are between 7nm and 35nm.