Semiconductor device having an output circuit for transmitting low-voltage differential signals

Claim 2

The semiconductor device according to claim 1, characterized in that said control unit comprises a differential amplifier (31, 42) which has a noninverting input, an inverting input, and an output, said noninverting input being connected to the drain of the second field-effect transistor (29, 40), the second voltage being inputted to said inverting input, and said output of said differential amplifier being connected to the gate of the first field-effect transistor (28, 39).

Claim 3

The semiconductor device according to claim 1, characterized in that said output circuit further comprises an input terminal from which the second voltage is inputted to said control unit (31, 42).

Claim 4

The semiconductor device according to claim 1, characterized in that said first field-effect transistor is a p-channel field-effect transistor (29), said second field-effect transistor is a p-channel field-effect transistor (30), and said second voltage is lower than the first voltage.

Claim 5

The semiconductor device according to claim 4, characterized in that said output circuit further comprises a resistor (30) which has one end connected to the drain of said second field-effect transistor (29), and the other end of said resistor is connected to a line from which a third voltage that is lower than said second voltage is inputted.

Claim 6

The semiconductor device according to claim 1, characterized in that said first field-effect transistor is an n-channel field-effect transistor (39), said second field-effect transistor is an n-channel field-effect transistor (40), and said second voltage is higher than the first voltage.

Claim 7

The semiconductor device according to claim 6, characterized in that said output circuit further comprises a resistor (41) which has one end connected to the drain of said second field-effect transistor (40), and the other end of said resistor is connected to a line from which a third voltage which is higher than said second voltage is inputted.

Claim 8

A semiconductor device having an output circuit, characterized in that said output circuit comprises: a first p-channel field-effect transistor (72) having a source connected to a first line from which a first voltage is inputted; a second p-channel field-effect transistor (73) having a source connected to a drain of said first p-channel field-effect transistor, said second p-channel field-effect transistor being in ON state when said output circuit is operated; a first control unit (64) which controls a voltage at a gate of said first p-channel field-effect transistor when said second p-channel field-effect transistor is in ON state, so that a voltage at a drain of said second p-channel field-effect transistor is held at a second voltage lower than said first voltage; a first n-channel field-effect transistor (80) having a source connected to a second line from which a third voltage lower than said second voltage is inputted; a second n-channel field-effect transistor (81) having a source connected to a drain of said first n-channel field-effect transistor, said second n-channel field-effect transistor being in ON state when said output circuit is operated; a second control unit (65) which controls a voltage at a gate of said first n-channel field-effect transistor when said second n-channel field-effect transistor is in ON state, so that a voltage at a drain of said second n-channel field-effect transistor is held at a fourth voltage higher than said third voltage, said fourth voltage being lower than said second voltage; and a signal generator unit (45) which generates output signals, voltages of said output signals being controlled by said first control unit and said second control unit, so that high-level values of said output signals are equal to the voltage at the drain of said second p-channel field-effect transistor and low-level values of said output signals are equal to the voltage at the drain of said second n-channel field-effect transistor.

Claim 9

The semiconductor device according to claim 8, characterized in that said first control unit (64) comprises a first differential amplifier (74) which includes a noninverting input, an inverting input and an output, said noninverting input being connected to the drain of the second p-channel field-effect transistor, said second voltage being inputted to said inverting input, and said output of said first differential amplifier being connected to the gate of the first p-channel field-effect transistor, and wherein said second control unit (65) comprises a second differential amplifier (82) which includes a noninverting input, an inverting input and an output, said noninverting input being connected to the drain of the second n-channel field-effect transistor, said fourth voltage being applied to said inverting input, and said output of said second differential amplifier being connected to the gate of the first n-channel field-effect transistor.

Claim 10

The semiconductor device according to claim 9, characterized in that said signal generator unit (45) comprises a first inverter (50) which includes: a third p-channel field-effect transistor (52) having a source connected to a third line from which said first voltage is inputted, and a gate connected to the output of said first differential amplifier; a fourth p-channel field-effect transistor (53) having a source connected to a drain of the third p-channel field-effect transistor, and a drain connected to a first output terminal, ON/OFF state of said fourth p-channel field-effect transistor being controlled according to a first signal; a third n-channel field-effect transistor (54) having a drain connected to said first output terminal, ON/OFF state of said third n-channel field effect transistor being controlled according to said first signal; and a fourth n-channel field-effect transistor (55) having a source connected to a fourth line from which said third voltage is inputted, a drain connected to the source of the third n-channel field-effect transistor, and a gate connected to the output of the second differential amplifier.

Claim 11

The semiconductor device according to claim 10, characterized in that said signal generator unit (45) further comprises a second inverter (57) which includes: a fifth p-channel field-effect transistor (59) having a source connected to a fifth line from which said first voltage is inputted, and a gate connected to the output of the first differential amplifier; a sixth p-channel field-effect transistor (60) having a source connected to a drain of said fifth p-channel field-effect transistor, and a drain connected to a second output terminal, ON/OFF state of said sixth p-channel field-effect transistor being controlled according to a second signal, said second signal having a complementary relation to said first signal; a fifth n-channel field-effect transistor (61) having a drain connected to said second output terminal, ON/OFF state of said fifth n-channel field-effect transistor being controlled according to said second signal; and a sixth n-channel field-effect transistor (62) having a drain connected to a source of said fifth n-channel field-effect transistor, a source connected to a sixth line from which said third voltage is inputted, and a gate connected to the output of the second differential amplifier, wherein said second inverter (57) outputs an output signal which has a complementary relation to an output signal output by said first inverter (50).

Claim 12

The semiconductor device according to claim 9, characterized in that said output circuit further comprises a resistor unit (66) which interconnects the drain of the second p-channel field-effect transistor (73) and the drain of the second n-channel field-effect transistor (81).

Claim 13

The semiconductor device according to claim 12, characterized in that said resistor unit (66) comprises a first resistor (83) and a second resistor (84) which are connected in series, an intermediate voltage between said second voltage and said fourth voltage being inputted to a connection point (85) between said first resistor and said second resistor.